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Related tags
  • AArch64
  • AMBA
  • Armv7-A
  • Armv8-A
  • AXI
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Forums

  • Classic processors forum

    Arm classic processors include the Arm11, Arm9, and Arm7 processor families.
    96 questions
    Chris Shore
    RE: how to utilize interrupts in arm9 processors..? what is residing inside ISR..? over 6 years ago
  • Cortex-A / A-Profile forum

    Users of Arm processors can be all over the planet, and now they have a place to come together. The processors community is the place to be all things processor-related.
    1,151 questions
    raks8877
    RE: translation table APTable permission problem 1 hour ago
  • Cortex-M / M-Profile forum

    The Cortex-M processor family is optimized for cost and power-efficient microcontrollers. Cortex-M35P, Cortex-M33, Cortex-M23, Cortex-M7, Cortex-M4, Cortex-M3, Cortex-M1, Cortex-M0+, Cortex-M0
    611 questions
    Jacek Wywrót
    Bus Fault when configuring cross trigger matrix / CTICONTROL 1 day ago
  • Cortex-R / R-Profile forum

    Cortex-R series processors deliver fast and deterministic processing and high performance, while meeting real-time constraints. Cortex-R52, Cortex-R8, Cortex-R7, Cortex-R5, Cortex-R4.
    68 questions
    Peter Rielly
    RE: FPU version in cortex-R52 5 days ago
  • DesignStart forum

    Discussion about custom SoC design with Arm IP through the easy-access DesignStart program.
    159 questions
    TinyLabs
    Cortex-M3 softcore minimal SoC 23 hours ago
  • TrustZone for Armv8-M forum

    Your first stop for all information regarding Arm TrustZone for Armv8-M, which brings security to the smallest of Arm Cortex processors by means of hardware-enforced isolation. Keep up with leading-edge information and get your questions answered.
    84 questions
    EugeneH
    MPU_S and cmse_check_address_range 1 month ago
All questions in this Community
  • Not Answered

    Global variable initialisation problem 0

    • Cortex-M3
    133 views
    0 replies
    Started 18 days ago
    by Maitland
  • Not Answered

    Illegal Instruction arm926ej-s Linux 0

    • Embedded Linux
    • arm926ej-s
    145 views
    0 replies
    Started 19 days ago
    by Leonidus
  • Not Answered

    Cortex-M3 Registers 0

    375 views
    4 replies
    Latest 20 days ago
    by Andy Neil
  • Not Answered

    Speculative data fetching on ARMv7-M 0

    • Armv7-M
    • Cache
    425 views
    2 replies
    Latest 20 days ago
    by MikeRobo
  • Not Answered

    Cortex-M3 Registers 0

    1339 views
    10 replies
    Latest 20 days ago
    by Fabiano Junqueira
  • Not Answered

    Design Start standard cell libraries have DRC errors in 45 RF SOI? 0

    88 views
    0 replies
    Started 20 days ago
    by Travis6
  • Answered

    FPB BreakPoint(without Debugger) 0

    • Armv7-M
    • Debugging
    • Cortex-M4
    481 views
    3 replies
    Latest 22 days ago
    by 42Bastian Schick
  • Answered

    Make MPU be uniprocessor system 0

    1998 views
    3 replies
    Latest 22 days ago
    by 42Bastian Schick
  • Answered

    Trouble configuring MMU for 2MB block mapping 0

    • Memory Management Unit (MMU)
    2364 views
    1 reply
    Latest 22 days ago
    by jcal93
  • Not Answered

    unable to wake up from power down mode in lpc2148 using external interrupt 0

    • Arm7tdmi
    • 16 (External Interrupt 0)
    447 views
    1 reply
    Latest 22 days ago
    by Andy Neil
  • Not Answered

    axi ordering 0

    2687 views
    5 replies
    Latest 23 days ago
    by Colin Campbell
  • Not Answered

    How to write to DHCSR register in Cortex-M 0

    • CoreSight Debug and Trace
    • 12 (Debug Monitor)
    • Cortex-M
    251 views
    2 replies
    Latest 23 days ago
    by 42Bastian Schick
  • Answered

    System wide cache flush 0

    • Cortex-A35
    • Cache coherency
    • Armv8-A
    • Cache Management
    2234 views
    5 replies
    Latest 25 days ago
    by Norbert Goldstein
  • Answered

    ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell 0

    1953 views
    3 replies
    Latest 26 days ago
    by jpthibault
  • Not Answered

    Exec latency for ASIMD instructions taking the V pipelines 0

    2348 views
    2 replies
    Latest 27 days ago
    by sjub
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