I have a question arout ARM CPU DSB/DMB
If I want :
1.write address A
2.read address B
Because of ARMv8 is Weak Consistency, the processor may execute in this order:
1.read address B
2.write address A
If I wand keep the program order, I need add DSB/DMB:
2.DSB/DMB
The read and write addresses in the above example are independence.
The question is if write/read cmd is address dependency. For example, I read a data from CSR and store it in DRAM, and then read the data in DRAM to next operation:
3.read address A
Do I need add DSB/DMB between step 2 and 3 to make sure the order?
3. need DSB/DMB ?
4.read address A
Hi Yunfei Zhu,
if you are considering only the PE executing this program and A is Normal memory, then the read from A will indeed see the value previously written to A in program order; no barrier is needed. This follows the Simple Sequential Execution model.
If I understand correctly, the read from B is reading a value from Device memory, which is later stored to A. I think we do not need to consider this access here, or did I miss something?
Best regards,
Vincent.
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