Blogs

Last month Google and Samsung released the first commercially available product using the ARM® Cortex™-A15 SoC design: the new Series 3 Chromebook. Not only does the Chromebook have the new…

I would like to share some news around one of the products we recently released, the V2P-CA15x2_A7x3.  This is a new member of the Versatile ™ Express CoreTile family and is the first ARM big…

The introduction of a new architecture as significant as ARMv8, or AArch 64, requires careful consideration of the impact to existing software! The good news is, the new architecture is compatible with…

The ARM architecture has been used for many years in mobile phones and electronic devices, but it is only relatively recently that the architecture has diversified into being used in laptops, tablets and…

Debugging and optimizing software is always a demanding job.  As today's  systems become more complex the task of providing a suitable debug and  trace solution becomes increasingly challenging - yet it…

This post goes into the juicy bits of what memory access ordering actually means and how this is handled in the Arm architecture.

This article is the first of a series on Arm fundamentals that will introduce various topics to help you get more familiar with the Arm architecture.

Page colouring is sometimes used as an optimization but as a result of the cache architecture some ARMv6 processors actually require the allocator use page colouring. This article will explain why the…

When writing code for Neon, you may find that sometimes, the data in your registers are not quite in the correct format for your algorithm. We explore this in further detail here.

In this article we will go through the steps required to setup Linux on the PandaBoard using files supplied from Linaro and also the further steps required to setup Linux for use with Development Studio…

The modern web is built primarily from three technologies: HTML, CSS and JavaScript. It is JavaScript that drives the interactive web; slow JavaScript means slow web pages. So today, a huge amount of effort…

In my first blog, we examined gave the historical context of the instruction set battles of ARM and x86, covering the RISC-CISC Wars in the PrePC Era and the PC Era. This blog covers Round 3, the PostPC…

This two-part blog gives a historical perspective on the ARM vs. 80x86 instruction set competition for three eras: PrePC (late 1970s/early 1980s), PC (mid 1980s to mid 2000s), and PostPC (late 2000s onward…

The 2010 ARM Technology Conference (Techcon) is taking place in Santa Clara next week. A large number of companies will be presenting their solutions to support development and optimization of products…

Wow it's that time again; our 4th release of Ubuntu on ARM is upon us. In the past we have provided a Freescale iMX51 image, a Marvell Dove image and a TI OMAP 3 image for Beagle Boards. This cycle…

This post is part of a series:Condition Codes 1: Condition Flags and CodesCondition Codes 2: Conditional ExecutionCondition Codes 3: Conditional Execution in Thumb-2Condition Codes 4: Floating-Point Comparison…

In the last article, I explained how to modify SWP code to make use of compiler intrinsics.  Using intrinsics hides the underlying detail needed to use the load and store exclusive instructions (LDREX…

Before ARMv6, the main synchronisation mechanism was the SWP instruction. SWP has two aspects, in a uniprocessor system it allows the read and write operations not to be interrupted between them.   In…

Once you move beyond short sequences of optimised Arm assembler, the next likely step will be to managing more complex, optimised routines using macros and functions.

This post aims to provide a simple introduction to Arm assembly language.

Ideally caches act as magic make-it-go-faster logic sitting between processor cores and memory banks. But there are cases where cache behaviour must be considered to get the desired result.