Mont-Blanc: Pioneering Arm-based HPC

Arm-based processors have traditionally dominated the mobile world of smartphones, tablets, and embedded IoT devices. However, in recent years, the increasing power demands of data centers, and in particular energy-hungry High Performance Computing (HPC) configurations, have made the use of Arm processors in servers ever more attractive. 

The potential offered by embedded processor technology in the HPC space was recognised back in 2011 by a consortium of European companies and institutions back, who decided to unite to pioneer an investigation of the usage of low-power Arm processors for HPC, in the Mont-Blanc series of projects. 

Partners

Arm, Bull (Atos) and the Barcelona Supercomputing Center (BSC) have been the three key partners throughout the various Mont-Blanc projects. However, over the years the projects have benefited from the involvement of a whole host of other European partners, bringing valuable expertise from research labs, academia and industry to contribute to the success of the program. 

Aims and Achievements

Mont-Blanc's overall aim is to build a scalable power-efficient HPC platform, based on low-power embedded technology. So far, three successive projects, Mont-Blanc 1, 2 and 3, have demonstrated the viability of Arm-based HPC clusters, with the world's first Arm-based HPC cluster being deployed in 2015, featuring over 2,000 mobile CPUs.

Of course, it's not as simple as just developing the hardware! The project has also created - from scratch - an Arm software ecosystem for HPC. This includes scientific libraries, a set of development tools for debugging, performance analysis and prediction, and automated kernal optimization. 

As part of the third phase of the project, Mont-Blanc 3, an exciting new prototype, Dibona, was built by Atos. It is based on 64 bit ThunderX2 processors from Cavium®, relying on the Arm-v8 instruction set. The prototype leverages the BullSequana X1000 infrastructure, including Direct Liquid Cooling – cooling with warm water. Three compute nodes will be integrated side by side in each BullSequana X1000 blade. The full configuration will ultimately include 48 computes nodes, ie. 96 Cavium® ThunderX2 CPUs, or 3000 cores. The blade model developed for the Mont-Blanc prototype will be commercialized by Atos as part of its BullSequana X1000 range, which was announced by Atos at ISC 2017.

The latest phase, Mont-Blanc 2020, started in December 2017, and aims to pave the way for a European scalable, modular and power efficient HPC processor, issuing recommendations for an Exascale Arm-based system.

Mont-Blanc at SC18

The Mont-Blanc team joined the community of scientists, engineers, developers, system administrators, educators, students, program managers, CIOs, and policy makers at SC18, in Dallas, Texas. The conference has an emphasis on education and best practices that deliver leading-edge insights to HPC users, advancing  the community’s state-of-the-practice. It embraces all aspects related to the practical use of HPC, including infrastructure, services, facilities, and large-scale application implementations.

The Mont-Blanc team exhibited as part of the European Exascale Projects booth, and took part in the sessions below:

Sun Nov 11

Workshop on Education for HPC

Including Two Mont-Blanc papers:

Mon Nov 12 Arm HPC User Group Workshop 
Wed Nov 14 Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs 
Thurs Nov 15 Arm SVE Hackathon: “Arm HPC Performance Today and Tomorrow”
powered by our Dibona prototype!

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