Logic-compatible Gain Cell eDRAM: A Real Alternative to SRAM

Embedded memories are a key component of IoT SoCs and recent applications such as Neural Network Accelerators. Unfortunately, SRAM based embedded memory has a large footprint which often covers more than 50% of the silicon area and is responsible for more than 50% of the power consumption. Furthermore, 6T SRAM cells are sensitive to variations and limit the potential for voltage scaling. Gain Cell embedded DRAMs (GC-eDRAM) rely on a bit cell that requires only 2-4 transistors with a dynamic storage node. As opposed to conventional DRAM, gain cells are logic compatible and require no additional process steps and can therefore replace SRAM at no additional cost. These memories further provide inherent two-port operation and have no direct leakage path. In this talk, Andreas Burg argues that GC-eDRAM is real replacement for embedded SRAM, providing both area and energy/power savings. He also shows that the technology is not limited to mature processes, but can also be scaled to nanometer nodes.

About Prof. Andreas Burg

Andreas Burg is an Associate Professor at Ecole Polytechnique Federale de Lausanne (EPFL), one of Europe's most vibrant and cosmopolitan science and technology institutions, where he leads the Telecommunications Circuits Laboratory in the School of Engineering

In 2000, he received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. In his professional career, Mr. Burg has been involved in the development of more than 25 ASICs. He is a member of the IEEE and of the European Association for Signal Processing (EURASIP). 

His research interests and expertise include: 

• Circuits and systems for telecommunications (wireless and wired)
• Prototyping and silicon implementation of new communication technologies
• Development of communication algorithms and optimization for hardware implementation
• Low-power VLSI signal processing for communications and other applications
• Digital integrated circuits
• Circuits for image and video processing 

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