A Research publication hat-trick!

I've had several opportunities to supervise student interns doing their Master’s or PhD degrees. As you can see from the map above, our interns come to us from all over the world, and three internships which I was involved in culminated in publications for Arm Research, enabling me to score a hat-trick in 2017! Through this post I'd like to give a big shout out to my collaborators for their great work, share a teaser of their publications (and show you where you can read the full works!) and encourage others to work with us in Arm Research. Let's take a look at the first of the three projects.

Synchronization Aware Traces | Karthik Sangaiah

Karthik developed a Valgrind-based tool to trace Open MP parallel applications, at a time when Valgrind support for Arm v8 was still under development. The traces are useful for quickly and accurately predicting scalability performance for multi-core systems. Nearly two years after his internship ended, we submitted a paper to the TACO journal and it got accepted. The credit goes to Karthik for chasing team members to run experiments and for persevering through three rounds of reviews. He is a very deserving first author of this journal paper! Shown below is a plot from the paper, followed by details of where to find the full paper.

Figure 1: SynchroTrace (ST) simulations with both ArmV8- and x86-based traces are consistent with the scaling performance trends of gem5 in all of the four strong-scaling benchmarks, namely CoMD, Graph500, Lulesh and XSBench.

Publication details

Title: SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads

Authors: Drexel University: Karthik Sangaiah, Michael Lui, Baris Taskin; Arm Ltd.: Radhika Jagtap, Stephan Diestelhorst; NVIDIA Corporation: Siddharth Nilakantan; Intel Corporation: Ankit More ;Tufts University: Mark Hempstead

Journal: ACM Transactions on Architecture and Code Optimization (TACO)

Download the paper

BarrierPoints Across Architectures | Alexandra Ferrerón

Alexandra joined us as a HiPEAC intern and implemented a BarrierPoints-based cross-architectural methodology. After finishing the internship, she continued analysis on the performance data she gathered during her time at Arm. My colleague Roxana Rusitoru who was Alexandra's supervisor for this internship, saw the potential for a publication. A few Arm colleagues keen on the work helped run additional experiments and write parts of the paper. About a year later, the paper got accepted at the ISPASS conference. The figure that follows shows potential simulation speed-up. To know more please check out the full paper (details below).

Figure 2: Potential simulation speed-up for applications in which we can predict the performance of full application execution by running shorter representative sections.

Publication details

Title: Crossing the Architectural Barrier: Evaluating Representative Regions of Parallel HPC Applications

Authors: Universidad de Zaragoza: Alexandra Ferrerón; Arm Ltd.: Radhika Jagtap, Sascha Bischoff, Roxana Rusitoru

Conference: 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

Download the paper

DRAM controller power model | Omar Naji

Omar was pursuing his Master's degree at the University of Kaiserslautern and the Memory and Systems Research group that I work in has had a long-standing collaboration with the university. Omar’s internship topic was modelling power-down modes in the DRAM controller model of the gem5 simulator and he was supervised by my colleague René de Jong. The work was in a preliminary stage when he finished his internship. Post that a few colleagues in Arm Research spent a good amount of time on validation and refinements. In this way, although Omar moved on to do other things, we were able to eventually publish the work at the MemSys conference. We also up-streamed the code to the public repository of gem5 to give back to the research community. The figure below shows that there’s no such thing as a free lunch – in each case we get significant energy savings after enabling the power-down modes, but that is accompanied by a drop in the performance. Fortunately, the energy delay product reduces for each benchmark, with 10% reduction in the best case for FFT.

Figure 3 Percent energy savings and percent decrease in performance when the power down modes are enabled compared to the baseline system without these modes.

Publication details

Title: Integrating and quantifying the impact of power-down modes in gem5 DRAM controller

Authors: Arm Ltd.: Radhika Jagtap, Wendy Elsasser, Andreas Hansson; Fraunhofer IESE: Matthias Jung; University of Kaiserslautern: Christian Weis, Norbert Wehn

Conference: International Symposium on memory systems, 2017 (MemSys)

Download the paper

Arm Research Publications

In Arm Research we are free to publish non-competitive research where appropriate. We also publish competitive research once it is in a suitable IP position, for example this paper on Arm SVE. This enables us to engage with the computer architecture and related communities. Once again, kudos to Karthik, Alexandra and Omar and I invite students from all around the world to apply, work together and publish with us!

See current opportunities in Research