Supply Monitoring on 28nm & FinFET - The Challenges PosedIn this, the fourth instalment of the "Let's Talk PVT Monitoring" series I chat with Oliver King about voltage monitoring in modern SoCs and we discuss the challenges posed when monitoring supplies on 28nm & FinFET. As Moortec’s CTO, Oliver has been leading the development of compelling in-chip monitoring solutions to address problems associated with ever-shrinking System-on-Chip (SoC) process geometries. An analogue and mixed signal design engineer with over a decade of experience in low power design, Oliver is now heading up the expansion of Moortec's IP portfolio into new products on advanced nodes.
1) What are the issues with supplies on advanced nodes?
The supplies have been coming down, quicker than the threshold voltages which has led to less supply margin. In addition to this the interconnects are becoming thinner and closer together which is pushing up resistance and also capacitance. Compounding all of this is the usual increase in gate density seen with moving down the process nodes, which increases power per unit area.
2) What is the effect of these issues?
In short, it reduces the margin between a design working and not. Design of the layout, in particular, power grids, and careful analysis of power consumption and therefore IR drop has to happen as part of the design, not as a verification at the end.
Also, the need for in-chip supply monitoring, which then in turn controls the chip’s power scheme, is growing. The speed of response for a Dynamic Voltage Scheme (DVS) needs to be such that PMIC control systems can react to supply droops and ‘events’ accordingly without data loss or corruption within the chip. There is also the growing need for high accuracy monitoring to enable fine-tune DVS schemes, optimizing power consumption against particular performance profiles. Of course, such monitoring and control schemes must be robust, as overall power control of the chip is at stake.
3) What about FinFET nodes, they have less leakage, right?
There has been a well publicized swing in power consumption with the move from 28nm to the first FinFET nodes, where on 28nm power consumption was dominated by leakage, on FinFET the power tends to be dominated by active switching. Whilst there are obvious benefits to that, there are some subtle effects which need to be considered.
If we consider a thermally stable environment, then leakage is essentially a DC current where, the only changes occur with power gating of blocks. This meant it was relatively simple to analyze IR drops around the chip and account for them. However, with the reduction in leakage brought about with FinFET, the active power is now dominant which is far more dynamic. This makes it harder to analyze IR drops.
4) What is the solution?
Depending on the complexity of the end system it may still be possible to design enough margin to cover supply drops, however, the cost of doing so is becoming too high for many applications, as it leaves too much performance on the table for all but the worst corner of silicon.
As such it is becoming more and more common to include some sort of supply measurement circuit within a chip which can allow for real in circuit measurement of IR drops and supply levels at certain points across the die, and in many cases this information is being used to then feedback control to external PMICs.
5) How does Moortec address those requirements?
Supplies keep coming down, and with the emergence of several new low voltage processes coupled with the growth in IOT applications where designs are running at much lower supplies you end up in a position which is much closer to failure.
The Moortec Embedded Voltage Monitor is designed for IR drop analysis and accurate DC supply measurement. This means accurate measurement of IR drops using differential inputs as well as measurement of ground lift.
This can be used to monitor supplies coming in from off chip and accurately measures core supply domain voltages.
About the intervieweeOliver King is the Chief Technology Officer of Moortec Semiconductor. Before joining Moortec in 2012, Oliver was part of the analogue design methodology team at Dialog Semiconductor and prior to that was a senior design engineer at Toumaz Technology. Oliver graduated from The University of Surrey in 2003 with a degree in Electrical and Electronic Engineering.
About Moortec Semiconductor
Moortec Semiconductor, established in 2005, provide high quality analog and mixed-signal Intellectual Property (IP) solutions world-wide specialising in die monitoring. Having a track record of delivery to tier-1 semiconductor and product companies, Moortec provide a quick and efficient path to market for customer products and innovations.
For more information, please visit www.moortec.com.
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