Low Power and Its Future?

Five years ago, ARM R&D Fellows Dr. Robert Aitken and David Flynn predicted [LS1] several low power design and implementation techniques which were discussed in detail in their book (co-authored by Michael Keating, Alan Gibbons and Kaijian Shi from Synopsys) titled “Low Power Methodology Manual – For System-on-Chip Design” (LPMM). This manual has been well appreciated in the industry and has set the stage for low power designs.

Five years later in today’s high performance and low power chip designs, we seem to be using almost all of these low power techniques in automated flows: clock gating, power gating, multi-Vt, multi-VDD and adaptive scaling in the form of Dynamic Voltage and Frequency Scaling (DVFS) or Adaptive Voltage Scaling (AVS). The LPMM also discusses the importance of selecting physical IP to support the goals, specifically the low power goals, of a given design. Just as low power techniques are evolving, so too is the physical IP used to implement these techniques.

FinFETs are great devices because they provide higher mobility, reduced body effect, and reduced device capacitance. This enables both high performance and lower power. The improved Ion/Ioff ratio makes the FinFET a more efficient switch. Isn’t that great? It will be very interesting to see how these well-proven low power design techniques such as DVFS are deployed when we move down to 16nm and below with FinFETs.

Last year I had an opportunity to present “Low Power Design with ARM Physical IP and POP IP” at a low power technology summit event, hosted by Cadence. It was a packed auditorium with an audience of approximately 200 designers, technical managers and architects of Low Power SoCs. The day started off with a visionary key note speech from Dr. Jan Rabaey from the University of California at Berkeley. The following are some of my key takeaways from this event and these techniques are certainly going to buck the trends for the future of low power. Continued voltage scaling (because power is proportional to CV²); self-adaptation (self-timed circuits); “razorized pipeline”; statistical, or non-deterministic, computing (this sounds like some “random” fun); emerging devices (nanowires and of course FinFETs); NEMS (nanoelectromechanical systems) and energy proportional systems (for example thermal monitors, PVT sensors, leakage sensors and even aging sensors!). These very advanced low power techniques look so promising that an overall energy reduction of 10X could very well be achieved. As chip designers and system architects, we seem to be leaving performance and power on the table because we tend to over-margin in designing for worst case scenarios. Eliminating margins will result in zero margins and even “negative margins.”  This is where analog design techniques have to be incorporated into digital implementations to save power and thereby keep the globe green!

So you might wonder, what’s next?  Gone are the days where you design a digital chip for one PVT corner and for a worst-case scenario. Think about a chip where you can seamlessly control variations, change voltage, temperature and frequency with ease, saving a ton of power by going in and out of several different power-down or leakage-saving modes. Making use of analog techniques to lower power in digital circuits is truly a way forward, and the future looks even brighter and greener. What will the next five years bring?

Sathyanath (Sathya) Subramanian, Technical Marketing Manager, ARM, is responsible for technical marketing for POP^TM Products and is part of ARM’s Physical IP Division. Sathya recently joined ARM, bringing more than 15 years of high-performance/low-power ASIC/SOC design and implementation experience. He holds MSEE and MBA.