The annual Design Automation Conference (DAC) was held last month, and what a show it was! If you recall, back in February, I talked about TSMC and ARM’s first tape-out with the ARM Cortex-A57 and Cortex-A53 processors. At DAC, we presented more data, as well as projections that show TSMC’s 16nm FinFET+ process can provide up to a 15% boost in performance from the 16nm FinFET process, or a 30% reduction in power at the same speed. While the “big” ARM Cortex-A57 could hit a frequency of over 2.5GHz, what was even more impressive was that it’s “LITTLE” counterpart, the ARM Cortex-A53, could operate at points that consume nearly 1/10th the peak power of the “big”. For our customers that are designing premium mobile this is great news, since these results show that high frequency can still be achieved while taking advantage of the power savings that the big.LITTLE architecture provides.
As 64-bit designs in mobile and enterprise become more prevalent, the primary target is not just maximum frequency. There are always some power considerations that need to be met. As the graph below shows, using the big.LITTLE processors such as ARM Cortex-A57 and Cortex-A53 allow flexibility for the SoC designer to target various frequency and power targets. Manufacturing at TSMC 16nm FinFET+ provides the highest performance SoCs for premium mobile or enterprise applications. Even while some next generation mobile designs require reduced voltage domains down to 0.7V, you can see that the Cortex-A57 can hit over 2.1GHz (@TT / 85C) at those reduced voltage levels. This high frequency, combined with the Cortex-A57’s capacity to deliver more performance per MHz results in top of the line performance while staying well under the 750mW budget. It also shows the extensive dynamic range of computing performance that a big.LITTLE configuration can deliver in a mobile power budget.
The 16nm FinFET+ process is further evidence of TSMC’s commitment to improve the ecosystem to deliver to both ARM and TSMC customers best-in-class manufacturing along with best-in-class processors. Some of the design challenges that were addressed during the collaboration effort include:
Timely collaboration is the key to understanding these challenges early, and providing solutions both in the process technology and physical IP, and enabling the manufacturing ecosystem. Starting with the first ARM Cortex-A57 tape-out, then building on that with Cortex-A57/Cortex-A53 big.LITTLE tape-out, our collaboration with ARM has resulted in an optimized IP ecosystem that customers can take to market quickly. Our customers have planned multiple tape-outs this year in 16FF+, and more big.LITTLE based designs to drive next-generation mobile applications!
What is size for the L2 cache in this chip(2.5GHZ)?