Hello there!
At this year's TSMC OIP event, I presented “Optimizing Cortex-A57 for TSMC 16nm FinFET” and it was a packed auditorium.
I would like to thank ARM, TSMC and Cadence for such an impressive colloboration in making sure that we ready the ecosystem for
our customers to deploy 16FF successfully. Special thanks to ARM Hsinchu Design Center (Taiwan) for pulling this off.
It was a fabulous experience. I presented this for 25 minutes and the moment I stepped out of the podium I was pleasantly surprised with several folks (customers) surrounding me and congratulating me for the talk and asking interesting questions. Each customer had their own very specific questions ranging from 16FF PDK version, Metal stack down to the nitty gritty implementation details of Cortex-A57 such as Power, Performance and Area (PPA). Well taping out such a large design (such as Cortex-A57) on 16FF and productizing the RTL2GDSII flow was definitely a big deal and we all should be proud of such a technological achievement.
For those people who had missed the presentation, following is a quick rundown of the details. Please do ask questions or post follow on discussions related to this topic.
There were two phases to this project. In Phase 1 we implemented a unicore Cortex-A57 with some peripheral circuits and R&D macro blocks (PVT sensors etc.,). Please note that the objective was not about hitting a particular Performance goal, but the intent was to enable the 16FF ecosystem. We had flushed out the whole flow and we are proud to say that the chip is actually working slightly above our sign off target. This proof points that our sign off methodology for 16FF was indeed pretty robust and very solid.
Phase 1 Design (Chip is back in the lab and I heard it is working and alive.. Great job!)
Cortex-A57 Floorplan (MP1 Cortex-A57 on 16FinFets)
For Phase 2, we are targeting a tape out in Q4 2013. This would have a big.LITTLE sub-system with both Cortex-A57 and Cortex-A53. The design team is shooting for higher frequency targets compared to Phase 1 development. Implementing such a big and complex chip on 16FF is a real big challenge given that the PDK, Cadence tools, Cortex-A57 RTL, and ARM Artisan 16FF Physical IP are all still undergoing perfection...
Phase 2 Design (This will have both Cortex-A57 and Cortex-A53 in a '2+4' configuration)
Following is quick summary of our collaboration model.
Our collaboration model (2 year engagement with several significant milestones)
In summary, a big thanks to TSMC and Cadence for making this technology real and available so our customers could enjoy the fruits of our labor. Job well done ARM!
Following are some of the key takeaways from this presentatio
1) FinFets are here and they are real. FinFets are optimized for both Performance and Power.
2) Cotex-A57 is a pretty cool and a Highest Performance/Watt v8 core
3) Thanks to the continuous Collaboration amongst (TSMC,CDN,ARM) for making all this happen.
4) ARM is enabling you with the most advanced Physical IP on 16FF. Thanks to ARM PIPD for staying ahead of the game.
Now I have a request for my fellow SOC Implementation Engineers. Let us go ahead and take full advantage of these technologies and design the next generation ARM based SOCs on FinFets!. We have revolutionized the Mobile space. Let’s do the same thing on the enterprise space as well.
Sathyanath (Sathya) Subramanian, Technical Marketing Manager, ARM, is responsible for technical marketing for POPTM Products and is part of ARM’s Physical IP Division. Sathya recently joined ARM, bringing more than 15 years of high-performance/low-power ASIC/SOC design and implementation experience. He holds MSEE (Wright State University) and MBA (Santa Clara University).
Great job!