During the ARM® -Mentor® seminar Tuesday, July 17, the nearly 100 attendees heard about the goals and ambitions of the long-term partnership between Mentor and ARM to improve testing of ARM cores and memories. Steve Pateras, product marketing director for silicon test at Mentor, presented first. He described the conditions that are driving new strategies for test and repair. It made me recall one of my favorite Benjamin Franklin quotes: "I didn't fail the test, I just found 100 ways to do it wrong." The complexity of testing modern SoC designs at advanced nodes, with multiple integrated ARM cores and other IP, opens up plenty of room for error. Both ARM and Mentor realized that their customers were integrating single or multiple ARM processors into their SoCs, and teamed up to provide a fully automated DFT strategy. They've been working closely for over 7 years. They presented their first full DFT reference flow for the ARM Cortex™ A-15. The flow includes documentation and command scripts for test insertion, synthesis, and automatic test pattern generation. The reference flow is available now for the ARM Cortex-A15, and will be available for newer ARM processors going forward. The second presenter was Richard Slobodnik, design-for-test engineer at ARM. He described the ARM core architecture and discussed how ARM has enabled improved test of memories and their shadows through two main areas:
In his presentation, Mr. Slobodnik also gave a nice review of the history of ARM core test strategies that eventually led to the standardized MBIST Shared Bus interface. Blocks with a shared bus and with memories on the bus (memory clusters) have a shared test interface to the bus (see the figure below).
The shared bus lets multiple memory arrays be serviced with a single BIST interface. This means you don't need a BIST wrapper for every memory block. They thoughtfully added these so they don't impact design performance, and so the customers can run at-speed tests. Mr. Slobodnik identified some of the problems that have arisen over the years of developing the shared bus flow, including the difficulty of manually creating the BIST input libraries. Mentor added automation to solve that problem. Another snag is in not being able to trace memories behind the shared bus. This could result in missing some of the memories during BIST insertion. A workaround was described using Mentor's ETChecker tool, and Mentor is working on providing fully automated support.
A key message I got from this seminar is not only about the complexity of testing SoCs, but that success for the designers depends on extensive cooperation between EDA and IP vendors. Mentor and ARM realize that for their customers to succeed, they must maintain a true partnership for developing.
To learn more, check out these resources:
Mentor whitepaper: High Quality Test of ARM® Cortex™-A15 Processor Using Tessent® TestKompress® ARM Partner product description: Tessent MemoryBIST
If you are using an in-house solution for ARM CPU BIST, what are your main concerns?
Guest Blogger:Beth Martin is a senior writer for Mentor Graphics. She has 14 years experience writing about physical design, test, and manufacturing for both EDA companies and for science and engineering magazines.