Semihalf's ARM64 blog #1: The FreeBSD on the 96 CPU ARMv8 SoC

Semihalf is happy to present the first blog post from the planned series of topics covering interesting facts about porting FreeBSD to ARMv8 architecture.

We're glad to announce that the Cavium ThunderX system has become the first ARMv8 hardware that runs FreeBSD.

Motivations and goals

FreeBSD is undoubtedly the most popular BSD operating system available.

Unlike Linux, it is released under a permissive BSD license and as a complete system distribution (this includes not only kernel but also base root file system and development tools).

One of the main areas of FreeBSD deployment is server market. It is therefore substantial for the FreeBSD community (developers and users) to keep up with growing interest in ARM-based servers. This idea was a motivation for Semihalf to pick up the gauntlet and bring FreeBSD to one of the most exciting ARMv8 platforms out there.

The newly introduced support was based on initial foundational work submitted by Andrew Turner and Robin Randhawa, with emulation as the primary target and is a joint work of Semihalf team, Andrew Turner, ARM Ltd., Cavium and The FreeBSD Foundation.

About the hardware platform

The Cavium ThunderX is currently the most advanced implementation of ARMv8 architecture. A single chip incorporates all features that are crucial for  modern server applications:

• SMP scalability up to 48 cores per socket (2-socket configuration gives as many as 96 cores)
• fast DDR3 ECC memory controllers with up to 128GB per socket
• top-performing network interfaces, configurable to support 1/10/20/40GbE over fiber or copper links
• variety of fast IO interfaces: PCIe 3.0, SATA 3.0

Semihalf contribution

Semihalf focus and responsibility was making FreeBSD work on ThunderX as the best performing chip in the FreeBSD/ARM64 world. From the beginning, our goal was to create a user-accessible support that could be taken from the FreeBSD-HEAD branch and utilized on the actual, ARM server.The work done includes:

• Stabilizing the machine dependent kernel parts to work on an actual hardware. Before, all development was done in virtualized environment, like QEMU or ARM FastModels. Interacting with the hardware allowed to find a full variety of very nasty bugs within the ARMv8 base system.
• Providing support for “extreme” SMP (Symmetric Multi-Processing) on ARM FreeBSD. ThunderX is the first machine that offers up to 96 CPU cores for the operating system. Previous ARM devices did not exceed 8 core count. Pushing it to its limit appeared to be a very interesting task.
• Implementing or enhancing existing drivers for basic subsystems. The most interesting are:
  • GICv3 and ITS (Interrupt Translation Services) - provide the FreeBSD with support for completely new approach to interrupt controllers and message signalled interrupts.
  • PCIe - add support for Cavium implementation of PCIe controller
  • Virtualized Networking Interface (VNIC).

The platform offers ultra-fast, virtualized networking interfaces (1Gbps, 10Gbps, 20Gbps, 40Gbps) with a richful set of functionalities, including SR-IOV with up to 128 virtual functions.

Future of FreeBSD on ARMv8

The ARMv8 architecture and ThunderX system is intended to be the Tier-1 platform for the FreeBSD. This means that FreeBSD will maintain the ongoing support for ARM64 and will provide application packages, etc. in a manner known from the other Tier-1 platforms (I386, AMD64).

All integrations are targeted to FreeBSD-11- STABLE which is going to be released in 2016. By that time all work done by Semihalf will be fully integrated into the FreeBSD tree.

About Semihalf

Semihalf creates software for advanced solutions in the areas of platform infrastructure (operating systems, bootloaders), virtualization, networking and storage.  We make software tightly coupled with the underlying hardware to achieve maximum system capacity.

Technologies developed by Semihalf power a wide range of products, from consumer electronics to cloud data center elements and carrier-grade networking gear.