A wide variety of applications will be impacted by the massive trend which is broadly named as the "Internet of Things" (IoT). Even if some may consider this term as being overused, and newer marketing names arise trying to replace it, there is the undeniable fact that connecting devices which used to be unconnected can make them act smarter, more efficient, and we will see more and more interactions between them. This goes beyond traditional electronic devices. Objects which did not include electronics are also likely to eventually embed more intelligence, hence electronics, to allow them to communicate.
In order to turn this concept to reality and mass deployment, there are many challenges to be addressed. A major area where both ARM and SuVolta are contributing is on the power side details of which were announced this week. We all want more connected devices and objects, but no one wants an equally higher usage of environment unfriendly batteries, nor the high maintenance cost of replacing them often, or even at all. Not only because of the convenience but also some enclosures might not allow it or the device may not be accessible.
ARM has been striving since it was founded to develop ever more energy optimized processor architectures and implementations which made its success. For example the power consumption of the ARM Cortex-M0+ in a basic configuration requires less than 9.8µW/MHz to run (see my recent blog). And it takes even more to achieve the energy efficiency needed at system level to run wireless sensors with a 10 or even 15 years battery lifetime, or enable power consumption compatible with energy harvesting sources which deliver in the range of 10 to 100µW per cm2 (see related EETIMES article). Even if the device is only operating periodically, part of the electronic system will have to be always on, either to wake-up the main functions (e.g. processor), and/or to retain the application context and enable instantaneous wake-up. Depending on the power profile of the application this latter can be more energy efficient than a so called "cold reset" from a full power down.
The DDC technology developed by SuVolta is therefore a very interesting complement to ARM ARM Processors. As demonstrated by the trials made on a Cortex-M0+ processor-based system, the dynamic consumption can be halved compared to using standard low-power process transistors. Knowing the invention and efforts our teams had to put together into the design of the Cortex-M0+ processor to reach a 30% dynamic power reduction compared to Cortex-M0 processor, we can only say "hats off" to SuVolta's achievement. The improvement brought by the DDC technology can be scaled to any of ARM processors, including our most energy efficient Cortex-M0+ processor.
The DDC transistor used to build the Cortex-M0 processors, include four doping layers in the silicon substrate under the transistor gate oxide. The top layer is a low-doped channel layer usually made by silicon epitaxial deposition. This layer dramatically reduces VT variation (σVT) by reducing random dopant fluctuation (RDF). The VT setting layer enables multiple threshold voltages without adding dopants to the channel region. The screening layer terminates the depletion layer in the channel to provide a uniform depletion layer and excellent short-channel effects. The punch-through layer reduces sub-channel leakage. The deep layers combine to produce a strong transistor body coefficient that enables many circuit-level power reduction techniques.
Equally important is the DDC reduction of the static power by a factor two. A large number of IoT applications are likely to remain in standby mode most of the time, so static consumption cannot be neglected in the power budget. Application duty cycles in the range of up to 98% standby versus 2% active may be applicable, so in this context as soon as the active power ratio is significantly less than 50:1 than standby power, then standby leakages will have the biggest impact on the battery lifetime.
The power reduction is one advantage of SuVolta's DDC Technology. As shown on the figure below, other tradeoffs can be achieved, bringing higher performance levels at either matched power or voltage.
The DDC technology offers also power reduction or higher performance beyond the processor, as we mentioned earlier power consumption is a system challenge and not limited to the processor. In standby mode a part of, if not all, the SRAM may remain powered. Keeping the context and status of the application in the SRAM can be advantageous for fast application resume, and may cost less energy than booting the application from scratch and storing/reading application state in non-volatile memories. The trials made at 65LP also showed a reduction by a factor two of the SRAM static power, which here also will have a direct benefit on the battery lifetime.
As for many challenging targets, you are better off working in a close partnership with companies having different expertises and backgrounds to come to the best solution. ARM and SuVolta are collaborating to tackle the low power requirements of emerging and demanding IoT applications and demonstrated quantum leap improvements at the 65nm process node. We look forward seeing the first products that will take advantage of this promising technology and of our lowest-power by design processors.