Chinese Version 中文版 [原创翻译]关于Cortex-M你可能不了解的5件事
ARM Cortex-M processors are a global microcontroller standard, having been licensed to over 40 ARM partners including leading vendors such as Freescale, NXP, STMicroelectronics, Texas Instruments,Toshiba, Microchip, Analog Devices, Silicon Labs, Spansion... Using a standard processor allows ARM partners to create superior device implementations with a consistent architecture for software developers to suit a large variety of applications.
ARM Cortex-M uses the high density Thumb2 instruction set for an optimal blend of 16/32-bit instructions. As such, applications are smaller in size reducing the required flash memory which reduces power consumption. The Thumb2 instruction set on Cortex-M achieves more per byte than 8/16-bit devices thus delivering more performance per MHz. The processor is a Harvard architecture with a 3 stage pipeline with hardware instructions for divide, multiply and saturated math.
ARM Cortex-M was built for creating sophisticated applications in the embedded space. The 4GB memory map is fixed across the product family on purpose in order to simplify software migration. A memory management unit adds reliability to the system by restricting access of each task to its own memory space under system control. A nested vectored interrupt controller (NVIC) handles the low layer software setup necessary to respond to interrupts, thus removing the need for assembly entry and exit routines. The NVIC also handles various levels of pre-emption and priority. The Cortex-M processors support thread and handler modes with privileged and unprivileged access. This is another factor adding to software reliability by giving access to system resources only to authorized software running in a specific state.
A major concern for embedded applications is power consumption. The most power efficient system is where the software is designed to take advantage of the power saving features of the hardware. The Cortex-M processors have specific instructions that enable smart power management. Wait for Interrupt, Wait for Event, and SleeponExit are the foundation of power aware software design. These instructions are used to create power aware software architecture. There is no longer any need for polling loops that keep the processor awake. Events and interrupts occur; the processor wakes up to respond then goes back to sleep or deep sleep. Average power consumption is then drastically reduced.
ARM has an exceptionally broad ecosystem of 3rd parties supporting the Cortex-M processor family. The product line was designed to be coherent across processors to simplify the task for tool developers. Developers have a choice from over 26 Real-time Operating Systems, 13 IDE packages and 21 debuggers.
Real-Time Operating Systems (RTOS)
There is also a connected community with a rich environment to exchange information and an embedded software store to sell products The specified item was not found.
ARM Cortex-M processors were designed to give developers the most advanced software infrastructure while respecting the need for energy efficiency for embedded applications.
In the next episode, we will take a tour of the Cortex-M3.
A good overview, but I think the statement may be a little generalizing. For example, the last sentence of the second part "2 - Instruction set":
"The processor is a Harvard architecture with a 3 stage pipeline with hardware instructions for divide, multiply and saturated math."
1) Only ARMv7-M cores are of Harvard architecture, while v6-M is Von Neumann architecture.
2) All but Cortex-M0+ are implemented with a 3-stage pipeline, while Cortex-M0+ has only 2 stages.
3) Hardware divide instructions only exists on Cortex-M3/M4 (see Divide and Conquer).
4) Saturation instructions also exists on Cortex-M3/M4 only.