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Cortex-R Series Power, Performance and Area (PPA) implementation analysis whitepaper

Neil Werdmuller
Neil Werdmuller
September 5, 2014
1 minute read time.

Embedded processors are frequently compared through the results of Power, Performance and Area (PPA) implementation analysis. jatinnmistry and I have created a whitepaper that describes the specific details of the PPA analyses performed on the Cortex-R Series processors.

Often high-level figures are quoted for processors, for example http://www.arm.com/products/processors/cortex-r/cortex-r5.php under the "Performance" tab, shows top level details of the Cortex-R5 in a mainstream low power process technology (40nm LP) with high-density, standard-performance cell libraries and 32KB instruction cache and 32KB data cache - this shows the total area as 0.45mm2.


However, behind the top-level power, performance and area results there are many variables and details that can dramatically alter these figures. Different implementations target different configurations, for example the cache sizes or inclusion of the Floating Point Unit (FPU), and target different goals, for example aiming to achieve the highest possible frequency or the lowest possible area. The process and libraries used have a dramatic affect. The attached whitepaper describes the process we use to perform a PPA analysis for the Cortex-R Series processors.

The goal of the whitepaper is to describe, for those without really deep processor implementation knowledge, the many variables that should be understood to get real value from any PPA data presented to enable an estimation of the real PPA of your own proposed processor implementation and also to make fair comparisons between processors, both from a single IP partner or between processors from different processor IP vendors.

Any PPA data without understanding the details behind it is of very little value. We hope that you find it informative.

ARM Cortex-R Series PPA Whitepaper 08Sep14.pdf
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