Cortex-M7 Launches: Embedded, IoT and Wearables

Acquire fences aren’t always enough. See how LDAPR exposed unsafe interleavings and what we did to patch the problem.

Introducing Arm GICv5: a scalable, hypervisor-free interrupt controller for modern multi-core systems with improved virtualization and real-time support.

A high-level introduction to the Arm Architecture Machine Readable Specification (AARCHMRS) Features.json with some examples to interpret and start to work with the available data using Python.