Interview: How to solve the IP integration problem

Chinese version 中文版： 人物专访：如何解决 IP 集成问题

I recently had the opportunity to sit down with David Murray and talk about the current state of affairs for IP integration in the context of building systems. For those of you who do not know David, he is an incredibly enthusiastic technologist who previously held the role of CTO at Duolog before gaining the impressive-sounding title of IP Tooling Architect in ARM. An energetic and articulate man, he is always interesting to listen to and I hope you enjoy the interview below. Feel free to ask questions in the comment space below and David will answer them ASAP.

This blog post follows up on the interview I conducted with Norman Walsh a couple of weeks ago. Norman spoke about the history of IP integration and how it has evolved to the point we are at currently. You can read the interview here Interview: A brief history of IP integration

Hi David, what’s going on in the IP integration space?

Well - IP integration continues to be a key challenge in SoC development. We’ve seen consistent increases in IP reuse, IP configurability and system complexity within tightly bound schedules compound the problem of IP integration. The number of IP in  a system continues to grow, the complexity and configurability of that IP itself is growing and the overall integration scope is growing as it affects more and more teams from front-end to backend  e.g. software, RTL design, verification, physical implementation etc.

This is a problem area that we are very familiar with and have been architecting integration solutions over the last number of years.   One of the fundamental pillars of improving the IP integration process is the standardization of the data in the process. This is something that Norman Walsh has mentioned in his interview is that we need to standardize our IP data (particularly the interfaces)through the use of metadata. If an IP can communicate its interfaces in a standard way than that the whole IP and SoC integration processes a lot easier.  If we can have a formal definition (in some metadata format) of all the interfaces of an IP then we can use more automated intelligence about how it should be hooked up and enable other crucial flows.  For example being able to identify AMBA interfaces, clocks, resets, interrupts, DMA, debug and trace interfaces etc.  Also, it’s not just the hardware interfaces I’m talking about, it it’s equally important to have a good view of the hardware/software interfaces like the registers and memory maps within the IP.

So how is this interface information standardized?

Well, for me, the obvious first thing is to make it so that the IP actually uses industry standard protocols as much as possible such as AMBA (ACE, AXI, AHB, APB, etc).  These interfaces are quite configurable so it’s important to be able to define their content and configuration in a metadata format. The main standard that the industry uses is the IP-XACT format, originally developed under the SPIRIT consortium but now developed under Accellera.  This essentially specifies a definition in a machine-readable (XML) format that can describe the IP interfaces and memory maps as well as its contents and connectivity. We are currently working within ARM to increase the standardization of ARM IP so it will be easier to integrate.

As long as a design flow creates this IP-XACT then we can work from there and run queries on that IP-XACT. Because we know what the tool reads and interprets, we can work together with partners to help them define the necessary IP-XACT specs.

Fast IP integration requires standardized IP

That sounds great but how does it work with lots of different 3^rd party IP or a partner's internal IP?

ARM also produces IP-XACT standard bus definitions that can be downloaded from the ARM Website for anybody to use.  If other IP providers use these standard definitions then it will provide a much easier mechanism of connecting these IP in a sub-system or top-level.  Also, don’t forget that this is not just enabling more efficient integration – our partners will also benefit from the provision of better EDA solutions that can leverage this metadata.

So there’s a lot work being done in ARM at the moment?

This is something we’ve been working towards for the past 6 or 7 years, even within Duolog, because there is huge potential for reducing bugs and streamlining design and verification processes.  At the moment we’re very focused on increasing the level of standardization within ARM IP and even have an internal IP-XACT modelling definition group. We’re creating new bus definitions, new extensions and guidelines on IP-XACT usage and of course we’re leveraging ARM Socrates to create better IP-XACT flows. Also, from working in the Systems and Software Group at ARM we have a sub-system and SoC-level perspective so we’ve become avid consumers of IP-XACT which gives us a good feel for what our partners are experiencing. The main challenges that we face are probably fairly common in the industry. We’re trying to standardize all of the interfaces that we need in metadata format but firstly we need to understand all of the different stakeholders.

This is great because once we have standardized IP interfaces it makes the integration and verifications process significantly faster. However while you can standardize most interfaces with a relative minimum of fuss, we’re seeing a lot of IP blocks these days that can be tweaked in many different ways.  In some ways we see IP configurability as the biggest integration challenge.

The level of IP configuration that is available these days poses a problem with integration, because you can take the same IP block and configure them in different ways, and they will look and act totally differently based on this. So that makes it more difficult to then integrate successfully into a system.

I liken this to a mixing desk that you would have in a recording studio with hundreds of switches that can be turned one way or another to affect performance. The options enable designers to optimize their IP, but the amount of choice can also be confusing. What the user really wants is to be presented with the best configuration options for that particular IP block that represents the system constraints.

Multiple configuration options can often leave designers confused

So how are you tacking this configuration problem?

When we talk about IP configuration in general, there are three different types of configuration levels that an IP block can have. First off you have what is called ‘static IP’ which cannot be configured at all. This was what you would call ‘off the shelf’ IP that was more common in the past, where you would purchase it for a ‘plug and play’ type functionality. Nowadays even off-the-shelf IP requires a bit of user configuration according to each individual design.

The second type of configurable IP is a simplified version that has a fixed set of parameters that can be set. Having said that - it can be a challenge creating a configurable IP because let’s say for example you have 10 or even 20 parameters, the amount of possibilities makes it difficult to guarantee that your IP will work for every single configuration. Validation teams and modelling will ensure that the IP works fine for the most probable scenarios, but it’s hard to test for everything. You only have a finite amount of verification resources to ensure that it is all tested rigorously.

The third type of configurable IP is heavily dependent on the system for its configuration, an example of these would be system interconnects, debug and trace subsystems,  power,clock & reset, interrupts, I/O, memory systems. They are super configurable and the amount of permutations means you need a different type of strategy to properly handle these. Ideally you would have some form of highly intelligent solutions that can interpret the system requirements and interfaces so that users can easily configure these types of IP.  These are the challenges that we have been working through and steering the Socrates design environment into providing solutions in this area.

ARM are already providing a lot of IP in this area including bus interconnection IP such as ARM CoreLink NIC-400,  ARM CoreLink CCI-400 Cache Coherent Interconnect, and ARM CoreLink CCN-512 Cache Coherent Network) as well as ARM CoreLink GIC-500 and also CoreSight Debug and Trace IP. These IP will consume vast amounts of system connectivity e.g. a cascaded interconnect infrastructure and CoreSight Debug and Trace could consume upwards of 50% of a systems connectivity, so in some ways highly configurable IPs are one of the pillars to solving the integration solution. 

The new key ingredient that we are bringing to the table is to help manage the configuration of these IP so that it is aligned with its system context. If we can understand the contents of a system and its different interface requirements we can help to guide the configuration of IP.

How do we do this? – By having all system components in a metadata format, of course, and to have intelligent flows that can extract this information and perform this guided configuration – really it’s intelligent IP Configuration.

So this is how the IP integration problem can be solved?

Yes - The vision that we have been working towards with the ARM Socrates IP Tooling for the last number of years has been to create a ‘System in a Day’ by creating an intelligent IP configuration capability.  Back when we first released Socrates, over 6 years ago, the integration task was taking people many months to get an initial RTL netlist and several more months thereafter to get a viable system up and running.  With Socrates we began making significant reductions to that schedule, bringing it down to several weeks.  We saw however that each piece of IP was designed , built and integrated independently of each other. So for example the interconnect was built from a specification, and then people attempted to integrate it into the system from the same (probably outdated) specification.  The bottleneck of the ‘System in a Day’ was the creation and integration of these system-dependent IP. The solution that we centred in on was to seek an intelligent way of configuring these IP … within the context of their system. We are arriving at a solution to the IP integration problem through intelligent configuration of the IP itself. I believe that configuring every aspect of the system correctly is a highly effective way of increasing its overall connectivity. 

What we’re trying to do here is use the metadata to give a fast, correct configuration in a system context. What I mean by system context is that you can see how different system requirements have a knock-on effect on the configuration of each IP and the system as a whole. What that allows us to do is reduce the time that’s spent on actually integrating the parts into a system because 90% of that work will have been done through intelligent configuration. In order to realize our ‘System in a Day’ vision for IP integration we need to do it through intelligent configuration. You need to have a solution for these complex IP blocks so that they can reconfigure themselves as the system is being defined.

We’ve seen partners say that even just understanding the perspective of some of the more complex IP blocks within the system normally takes them several weeks to compile. In the past they have had to go through the TRMs and specs to understand what is required for the system.  We want to be able to provide this information instantly from the metadata of the IP in the system.

The IP integration problem will be solved through intelligent configuration

Verification is such a massive part of SoC design these days, how does Socrates fit into that story?

Going back to the IP-XACT metadata that I mentioned earlier, by working in this format we’re able to get a clear picture of the system  very early on and in an easily readable format (XML). We can then hand off this rich information about the system, its interfaces, the registers views and memory maps to our EDA partners and other ecosystem stakeholders.  Because the information is presented in a format that is standard and machine-readable they can work on verifying it immediately. For example Cadence Design Systems can take the metadata for its Interconnect Workbench and automatically creates a verification environment and out-of-box performance scenarios and analysis This feeds into our overarching goal of helping partners design and implement systems in a much shorter timespan.

This sounds very exciting for the future, but is any of that available today?

ARM Socrates is already a proven solution for IP standardization and integration and we’re now beginning to leverage an intelligent IP configuration methodology.  Now that we’re part of ARM we feel that there is a much greater value that we can bring to our partners as we’re working directly with the IP and can steer is standardization and streamline its integration. This is very exciting and you should see new solutions appear in the near future.

Final question for you here. IP Tooling Architect is an interesting title, how has your role changed from being the CTO at Duolog?

Well, when you are in a small company like Duolog – it’s more ‘roles’ than role.   I would have had to keep constantly tuned into our customers design flows and look for any hotspots in their development process. Once the main problems were identified, we had to work on envisioning and architecting a solution to this, and eventually, with a committed team, realizing a high-value product such as Socrates. That’s how we got into IP Integration – we didn’t chase it – it came to us, through our customers.   It was difficult however for a small company to carve out its niche so there was also a lot of evangelizing, writing white papers, blogs, presenting at conferences etc. and plenty of customer meetings.    Another one of the things I did within Duolog was to align ourselves with standards groups and try and progress them toward real solutions areas.  For a small company Duolog invested quite a lot of time and effort in driving the IP-XACT standard and this is definitely something I will continue to do within ARM, helping to progress both internal and industry standards for everyone’s benefit.

Now that I think about it, overall I have a pretty similar role in ARM.  The problem space is still IP integration – we’re still chasing the same dream of ‘System-in-a-day’ and I can boldly speculate that this WILL become  a reality – the big change is that now that we’re ARM,  we've got ARM IP in the equation and wow – that brings incredible potential.  Before, as Duolog, we had to partner with ARM to get limited access to the IP - Now we can work directly with the IP designers from a much earlier stage of development and facilitate intelligent IP integration from the bottom-up with standardised IP blocks – this will be a game-changer. 

OK great. Thanks for your time David

No problem, my pleasure. (Have I really been talking for 10 minutes?) -   I hope your readers find this interesting and ask them to leave a comment if they have any questions for me!

Additional information can be found with these 2 white papers:

• Solving Next Generation IP Configurability
• Leveraging IP-XACT standardized IP interfaces for rapid IP integration