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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 720 Questions
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  • Not Answered

    Forum FAQs 0

    • ARM Community
    3617 views
    0 replies
    Started over 4 years ago
    by Annie Arm Employee Badge
  • Not Answered

    Can MakeInvalid be issued by discarding the issuer's own dirty data? 0

    • AMBA 5 CHI
    • CHI
    82 views
    0 replies
    Started 2 days ago
    by Ioannis Tzanakis
  • Answered

    Can a WriteUnique be sent after CompDBIDResp but before CopybackWrData? 0

    • AMBA 5 CHI
    • CHI
    503 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Understanding Correspondence of 1-bit ACTIVE Signal to Different Power Modes in Arm®︎ Power Policy Unit Architecture Specification 0

    • PPU
    • q-channel
    728 views
    3 replies
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    I'm curious about how INTID calculation works. 0

    • GIC400
    • INTID
    322 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Debug Message Output Issue in RTL Simulation 0

    • printf
    • debug
    152 views
    0 replies
    Started 1 month ago
    by ele
  • Answered

    Write Hit in Shared State is there any way where i could do the write operation without wait in for invalidation ACK in ACE 0

    • AMBA
    • ACE
    • ACE-Lite
    • ACE 5
    706 views
    6 replies
    Latest 1 month ago
    by Kidilam Firoz
  • Not Answered

    Difficulty Integrating PARSEC Benchmarks with gem5 ARM - Seeking Best Practices 0

    154 views
    0 replies
    Started 1 month ago
    by RAJASEKAR LAKSHMANAN
  • Answered

    ACE:why writeunqiue/writelineunqiue cant overlap with writeback? 0

    • AMBA
    • ACE
    • Interface
    286 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    hello,problems that need to be confirmed on the AHBS interface of the Cortex-M7 processor. 0

    • Cortex-M7
    • Cortex-M
    • AHB
    146 views
    0 replies
    Started 1 month ago
    by ren tianpeng
  • Not Answered

    hello,I have confirmed the problem of using the sie-200 IP ahb synchronous bridge. 0

    • AHB2AHB
    145 views
    0 replies
    Started 1 month ago
    by ren tianpeng
  • Not Answered

    Assertion for channel dependency 0

    • AXI4
    164 views
    0 replies
    Started 2 months ago
    by Amit Mishra
  • Answered

    AHB Write Strobe calculation +1

    • AMBA
    • AHB2AHB
    • AHB2APB
    • AHB5
    • AHB
    1101 views
    4 replies
    Latest 2 months ago
    by Kartik Singh
  • Not Answered

    Cortex-R52+ TCM access width 0

    • tcm
    • Cortex-R52+
    198 views
    0 replies
    Started 2 months ago
    by Grace WANG
  • Not Answered

    I am a little confused on this website. If I am using the amba4 protocol, which document should I read? 0

    • AMBA
    • AXI4
    604 views
    3 replies
    Latest 2 months ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Cortex M85 Fast Model / TXEV & RXEV signals 0

    989 views
    1 reply
    Latest 2 months ago
    by Toshihisa Oishi Arm Employee Badge
  • Not Answered

    Coresight STM500 Required Address Space to support channel ID 0

    • Cortex-A53
    • System Guidance
    • Cortex-A
    • Debugging
    • CoreSight
    197 views
    0 replies
    Started 2 months ago
    by Daehwan Kim
  • Not Answered

    RF45SOI GPIO information 0

    • 45RF
    193 views
    0 replies
    Started 3 months ago
    by PETER CHENG
  • Answered

    AXI4 transaction 0

    3684 views
    19 replies
    Latest 3 months ago
    by Colin Campbell Arm Employee Badge
  • Answered

    CHI.F document typo issue in Table B4.14 0

    • AMBA
    • AMBA 5 CHI
    419 views
    1 reply
    Latest 3 months ago
    by Christopher Tory Arm Employee Badge
>
Topics being discussed in this forum
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