for Cortex-M0, M3 and M4, I can find the execution time in their Technical Reference Manual > Programmers Model > Instruction set summary 里面查看
but for M7 It said that I should go to <ARMv7-M Architecture Reference Manual.>
“The processor implements the ARMv7-M instruction set and features provided by the ARMv7E-M architecture profile. For more information about the ARMv7-M instructions, see the ARMv7-M Architecture Reference Manual.” -----《ARM Cortex-M7 Processor Technical Reference Manual》Programmers Model > Instruction set summary > Binary compatibility with other Cortex processors
But in <ARMv7-M Architecture Reference Manual.> I still can't find it. what should I do?
Arm don't publish a cycle timing table for the M7.
As many instructions are dual issued overall code performance/bench marking is probably more useful than trying to calculate timing by adding sequential instruction timing.
thanks for your reply. I am still a little confused. what's the dual issued? because all the other uP has given the cycles table except M7. Is there any official explanation for this issue?
you said benchmark is more useful for M7, do you mean that 'adding sequential instruction timing' is also more useful for other cortex device?
Thank you very much
Binary compatibility with other Cortex processors means that you can use instruction execution time (in cycles) for Thumb instruction set from previous technical reference manuals of ARM Cortex-M3 or ARM Cortex-M4. Read more about compatibility in ARM Cortex-M7 Processor Technical Reference Manual, chapter 2.3.1. Binary compatibility with other Cortex processors. ARMv7-M Architecture Reference Manual includes more detailed information about ARM and Thumb instruction sets.
But, is the compatibility just mean that the program is compatible rather than their execution cycle is the same?
I know the dual-issue means that for every instruction cycle it fetch 2 instructions. But during my debugging, I use STM32F746 and debug in Keil-MDK, it seems like that the execution cycle is the same with it in other cortex device. for example the MOV, MUL.... are all 12 state cycle(clock cycle), which is just a machine cycle. Is that means, the dual-issue doesn't work at this part?
Architecture of Cortex M7 pipeline is more complicated, than in previous M3,M4, but I think that operations of Thumb instruction set take the same time (in cycles) at the execution stage. Read about in-order and out-of-order execution. Cortex M7 has featute of in-order issue and superscalar pipeline with dynamic branch prediction (it can execute instructions in parallel).
So that, in practice is it harder to predict the execution time by calculation than the others?
You know execution time in cycles for instructions, but you should take into account another factors when you want to calculate execution time for some portion of code, such as how many stages in pipeline before execution stage, branch prediction, cache hit or miss. For real-time applications or functions it is better to use tightly coupled memory in such case you exclude factors of cache hits or misses, and you can meet time requirements for your functions. Do not forget about branches, when branch prediction miss occurred you have to calculate time for loading pipeline with instructions from branch address in code, in case of branch prediction hit you need to calculate only execution time for instructions.
Thanks, thank you very much