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[Cortex-A15/Arm7v]Is the way to disable the speculative memory accesses of L1

Dear Expert

We would like to disable the speculative memory accesses of L1.
Is the way to disable above function?

We found "I bit of SCTRL" controls the function of Instruction Caches.
If we negate that bit,  are both Instruction Caches and the speculative memory accesses disabled?

If we would like to disable the speculative memory accesses alone, how should we do?

We use the processor of A15 (revision  r2p2).

Regards.

Parents
  • I am sorry for my late reply.

    Explaining why we would like to disable speculative accesses, we encountered the problem that CPU accesses to forbidden addresses randomly when enabling speculative accesses and branch predictions.
    And we think that disabling them is the reasonable solution for that.

    However, as you pointed out, disabling them cause the negative side effect , which slow down the processing speed by about 50%.
    Considering about it, we decide to set the XN ranges in the MMU tables as you told us.

    We would like to set XN ranges in units of 4k bytes with MMU.  
    Although reading TRM for A15(https://developer.arm.com/documentation/ddi0438/e/Memory-Management-Unit/TLB-organization/L1-data-TLB?lang=en), we cannot understand how to make 4k tables and set XN for them.

    Could you teach me how to do the above?
    If there are some example codes about it, it is very helpful to tell us the link.

    Regards.

Reply
  • I am sorry for my late reply.

    Explaining why we would like to disable speculative accesses, we encountered the problem that CPU accesses to forbidden addresses randomly when enabling speculative accesses and branch predictions.
    And we think that disabling them is the reasonable solution for that.

    However, as you pointed out, disabling them cause the negative side effect , which slow down the processing speed by about 50%.
    Considering about it, we decide to set the XN ranges in the MMU tables as you told us.

    We would like to set XN ranges in units of 4k bytes with MMU.  
    Although reading TRM for A15(https://developer.arm.com/documentation/ddi0438/e/Memory-Management-Unit/TLB-organization/L1-data-TLB?lang=en), we cannot understand how to make 4k tables and set XN for them.

    Could you teach me how to do the above?
    If there are some example codes about it, it is very helpful to tell us the link.

    Regards.

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