Using LDREXD in a task/normal mode and STREXD in ISR

On a Cortex R,  where ldm/stm are interruptible, can i use ldrex and strex for double words to pass from ISR to a task in this way?

in ISR:

 STREXD,   //  Ignoring  (yes, dumping it)  if it actually failed to write , do no spin-lock or retry here at all

in Task :

  LDREXD   // load ..
  CLREX     // clear exclusion

One core  (2 in dual lock-step),  no sharing mem with other cores.  Will this work for automically write/read double words in the scenario one ISR feeding a task?

And yes, no buffering between them.

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  • I believe - from this ARM support forum - ldr/str ex have the inner/outer (don't know the exact term) concept, i.e:

    ldrex{ ldrex, strex} strex   <-- holds, i.e  the inner only unlocks the latest ldrex . So I don't think / agree about _ANY_ if that's what you meant.  In separate memory locations .

    But yea, if I'm into using atomic words of lesser size, then I'm better off to do just a typical ringbuffer to copy buffers, and that's not what I was wondering about.

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  • I believe - from this ARM support forum - ldr/str ex have the inner/outer (don't know the exact term) concept, i.e:

    ldrex{ ldrex, strex} strex   <-- holds, i.e  the inner only unlocks the latest ldrex . So I don't think / agree about _ANY_ if that's what you meant.  In separate memory locations .

    But yea, if I'm into using atomic words of lesser size, then I'm better off to do just a typical ringbuffer to copy buffers, and that's not what I was wondering about.

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