Hi Team, in cache.s file in uboot under path arch\arm\cpu\armv8, it was mentioned that if x0 = 0 then clean and invalidate and if x0 = 1 then only invalidate. I did not quite understood where the check is happening to decide on to clean and invalidate or only to perform invalidate. Also I did not quite understood how the caching is happening with all 4 levels?
I wanted some technical documentation for exceptions.s, cache.s which is present \arch\arm\cpu\armv8 path. Wanted to understand why align 11 and align 7 are used in exceptions.s. Also the processor reference manual has exception vectors of 12 but there are only 8 present in exceptions.s why? like wise wanted technical writeup for assembly files such as exceptions.s, cache.s, tlb.s.
Really appreciate your speed response.
Thanks in advance
Chaitan said:Wanted to understand why align 11 and align 7 are used in exceptions.s.
The reason can be found in the Armv8-A manual.