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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3624 Questions
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  • Not Answered

    Forum FAQs 0

    • ARM Community
    8710 views
    0 replies
    Started over 5 years ago
    by Annie
  • Answered

    Cortex-M85 & Cortex-M55 Core ID 0

    • Cortex-M55
    • Cortex-M85
    542 views
    3 replies
    Latest 13 hours ago
    by Mahmood Yakub Arm Employee Badge
  • Suggested Answer

    AXI5 0

    • AMBA 5
    79 views
    2 replies
    Latest 13 hours ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    Dormant state for debug 0

    • Debugging
    41 views
    0 replies
    Started 1 day ago
    by Yael Kanter-Weisman
  • Not Answered

    the issue of different execution times for the same assembly code on Cortex-A53 0

    234 views
    4 replies
    Latest 2 days ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Question about Snoop Response for SnpCleanShared using CHIE.b? 0

    • CHI
    135 views
    1 reply
    Latest 3 days ago
    by Ben Hicks Arm Employee Badge
  • Suggested Answer

    Does TCM configured as Strongly ordered memory have alignment alignment requirements? 0

    • Cortex-R5
    192 views
    3 replies
    Latest 5 days ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How AXI Handle unaligned transfer in FIX and INCR mode. 0

    208 views
    2 replies
    Latest 7 days ago
    by roshan ekre
  • Not Answered

    M33 parallel trace clock 0

    • Debug and Trace
    139 views
    0 replies
    Started 16 days ago
    by Yael Kanter-Weisman
  • Not Answered

    Behaviour of ERRSTATUS when injecting CE and DE via Pseudo Fault Generation. 0

    112 views
    0 replies
    Started 19 days ago
    by anoop
  • Not Answered

    Base Address of AHB-AP in DAPlite-2 0

    • Debug Access Port (DAP)
    140 views
    0 replies
    Started 23 days ago
    by RAGHU CHOWDAM
  • Not Answered

    Cortex-M7 Processor Accessing Illegal Address Interval Report RESEP=2'b11 0

    238 views
    2 replies
    Latest 28 days ago
    by yangfang
  • Not Answered

    The Cortex-R52+Processor has AIXM interface, AXI_FLASH interface performance 0

    101 views
    0 replies
    Started 28 days ago
    by yangfang
  • Not Answered

    AHB Write Access With wait states 0

    • AMBA
    • AMBA 3 AHB Interface
    • AHB
    241 views
    1 reply
    Latest 29 days ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    The HREADY signal connection issue in an AHB5 busmatrix 0

    162 views
    0 replies
    Started 1 month ago
    by yangfang
  • Not Answered

    DMA Controller PL230 - Why N is multiple for 4 in scatter-gather mode ? 0

    • DMA Devices
    • PrimeCell µDMAController (PL230)
    133 views
    0 replies
    Started 1 month ago
    by hk_007
  • Not Answered

    Question about the 64-bytes aligned granule access for write request with RO=1, in Server Base System Architecture, DEN0029J 8.0 0

    150 views
    0 replies
    Started 1 month ago
    by Junji Koyama
  • Suggested Answer

    NEED HELP 0

    279 views
    1 reply
    Latest 1 month ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    S-suffix in ARM Cortex M7 IT block 0

    159 views
    0 replies
    Started 1 month ago
    by Mr_M_from_G
  • Answered

    Unable to switch clock source after setting ACLK_CTRL.CLKSELECT to Clock Gate (Corstone SSE-710) 0

    • Corstone
    236 views
    1 reply
    Latest 1 month ago
    by Ronan Synnott Arm Employee Badge
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