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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3512 Questions
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  • Not Answered

    Forum FAQs 0

    • ARM Community
    8198 views
    0 replies
    Started over 4 years ago
    by Annie Arm Employee Badge
  • Answered

    How do I get a FVP_BaseR_Cortex-R52x2? 0

    • Cortex-R
    128 views
    3 replies
    Latest 4 days ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Hardware implementation of vector load/store instructions on the CM55 core 0

    • Cortex-M55
    • optimization
    • Cortex-M
    • Vectorization
    145 views
    0 replies
    Started 4 days ago
    by Oleksandr Tymoshenko
  • Not Answered

    Disable HW Prefetcher On Pixel 8 0

    • EL1
    • Android
    • EL2
    • AArch64
    • pixel8
    • Arm9
    • HWprefetcher
    • Linux
    190 views
    0 replies
    Started 5 days ago
    by Gal Kaptsenel
  • Answered

    Will these two different data storage methods and MPU settings affect CPU efficiency? 0

    • mmu
    • mpu
    • Cortex-A
    • Cortex-M
    117 views
    1 reply
    Latest 11 days ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    APB: Support Write Enable mask? 0

    • APB
    • Architecture
    • Memory
    182 views
    1 reply
    Latest 12 days ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Cortex A53 Cycle Counting, Single-Step 0

    • Armv8-A
    • Performance Monitor Unit (PMU)
    • Debug Access Port (DAP)
    109 views
    0 replies
    Started 12 days ago
    by Sahin Duran
  • Not Answered

    Is using WFI with PIT-based scheduler safe in bare-metal on S32K311? 0

    • timer
    • wfi
    151 views
    0 replies
    Started 17 days ago
    by nowkoes
  • Not Answered

    ARM Cortex-M3 Priority 0

    203 views
    0 replies
    Started 19 days ago
    by vignesh varadaraj
  • Not Answered

    A53 core not going into WFI sometimes. 0

    319 views
    2 replies
    Latest 26 days ago
    by Diptendu
  • Suggested Answer

    Clarification on Instruction Cache Availability in Cortex-M33 IP 0

    263 views
    1 reply
    Latest 27 days ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    How to know the APSEL number when there are multiple APs? 0

    • adi
    134 views
    0 replies
    Started 27 days ago
    by si huibin
  • Not Answered

    TF-M PSA Crypto Random 0

    • PSA
    • TF-M
    414 views
    4 replies
    Latest 29 days ago
    by Fran DP
  • Not Answered

    Unable to read currentel 0

    • a72
    • Armv8-A
    401 views
    3 replies
    Latest 1 month ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    SOC sensor chips 0

    120 views
    0 replies
    Started 1 month ago
    by Brahm
  • Suggested Answer

    Difference between System mode, User mode and Supervisor mode in Cortex R. 0

    • Cortex R
    311 views
    1 reply
    Latest 1 month ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    Cortex-R5F core unexpected fetch reserve address 0

    247 views
    1 reply
    Latest 1 month ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [ARM R52+] GIC distributor on R52+ with DCLS 0

    • GICv3/v4
    • Armv8-R
    303 views
    2 replies
    Latest 1 month ago
    by ShihHsun Chang
  • Not Answered

    Question about ITS Retry Behavior after Stalled MAPD Command 0

    266 views
    2 replies
    Latest 1 month ago
    by steve jeong
  • Suggested Answer

    AXI4 ordering Model. 0

    • AXI4
    310 views
    1 reply
    Latest 1 month ago
    by Christopher Tory Arm Employee Badge
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