Is the DesignStart Eval compatible with heterogeneous multi-core design, e.g. Cortex-M0 with Cortex-M3?

  • There are two main things to consider: the memory system and debug. The DesignStart Eval package contains the building blocks needed for the memory system, although designers would need to consider how to handle address 0x0, as each processor wants to boot from that address. The debug part is less straightforward however, and a company looking at creating a heterogeneous multi-core design is advised to use DesignStart Pro, as DesignStart Eval does not contain sufficient CoreSight debug IP to build a heterogeneous multicore debug system. Debug for multiple Cortex-M3's (only) is achievable, but there is insufficient IP to merge trace streams from multiple cores.