Chinese Version 中文版：通过智能配置进行系统汇编
The modern SoC is designed with many modular IP blocks that have been commercially licensed or reused from previous designs, along with some new proprietary components. Integrating all of the components has typically proven to be time-consuming and error-prone as designers stitch their SoCs together by hand or rigid and outdated scripts. Challenges also exist in the form of highly configurable IP blocks such as the interconnect fabric and debug & trace subsystem.
To address these issues ARM® launched three new tools today as part of an IP Tooling suite. They have been designed to solve challenges associated with SoC configurability and integration while reducing time to market with at least an 8x improvement in schedule.
The Socrates™ Design Environment (DE) is a complete tooling solution that handles the configuration and integration of ARM-based SoCs quickly and efficiently. It is through tooling that IP blocks can become greater than the sum of their parts, optimized for performance across the entire system.
There are also CoreSight™ Creator and CoreLink™ Creator, which are specialized tools that guide users through the configuration process of implementing a CoreSight debug and trace subsystem and CoreLink interconnect. The Creators focus specifically on these subsystems with many configurable pieces of IP that typically took months to configure and stitch currently.
The tools work together to enable ARM partners to configure and generate an SoC in days, not months. For example, the CoreSight Creator harvests data about the IP in the SoC, generates a CoreSight debug and trace subsystem description to match that is then fed back into the Socrates DE design flow, for integration into the overall SoC. When used together they deliver an integration experience that is seamless, from the configuration of individual components to the assembly of the SoC. The Creators use built-in ARM engineering intelligence to remove the need for expertise in the details of the CoreSight or CoreLink IP, allowing users to build integrate CoreSight and CoreLink IP in to their SoC with minimal engineering interaction.
All of the tools function by harvesting the IP-XACT description of each component in the system. The IP-XACT contains information on the registers, memory maps and interfaces, as well as master/slave relationships. The tools can effortlessly manage 100,000+ lines of connection meta-data per IP. Socrates DE then uses a simple rules-based methodology to capture design intent and automatically generate the connections. Whether it’s configuring a subsystem or the entire SoC, the Socrates tools work under the same premise. To give you an idea of how this can be achieved, let me take you through how it works using the example of a CoreSight subsystem.
Historically you would have had to stitch together a CoreSight subsystem (such as the CoreSight SoC-400) manually using AMBA Designer or hand crafted top-level RTL. With CoreSight Creator you double click the menu item in the user interface, which launches the tool and begins harvesting the system information. This means it is reading all of the IP-XACT in the entire system design (for example, Cortex processors, System Trace Macrocell, interfaces).
It will identify the typical interfaces needed to describe and specify a CoreSight subsystem to generate a High Level Specification (HLS). The HLS defines the type of system interfaces from the System IP and processors that need to come into and out of a CoreSight debug and trace subsystem. CoreSight Creator will help create this HLS very quickly and seamlessly for users.
High Level Specification of a CoreSight debug and trace subsystem
From there the tool can automatically run a Microarchitecture Synthesis and this will render out a microarchitecture of a CoreSight subsystem. The microarchitecture comprises the configuration specification of each CoreSight component and all interconnections to them. To do this today, system designers need to do it manually. This requires a very good understanding of the entire CoreSight catalog and CoreSight architecture.
With the schematic viewer on the user interface you can zoom in review the design by category: trace bus; debug access; timestamping; and cross-triggering. Even at that it is time-consuming and error-prone. The microarchitecture is rendered automatically so it removes the risk of error. For power users, the tool does permit manual editing of the microarchitecture so any capability, any configuration of the IP is available if required.
Schematic view of the Trace connections in CoreSight Creator
At each stage of the process there are multiple Design Rule Checks (DRC) that automatically check whether this is a valid microarchitecture and matches the HLS for the CoreSight subsystem. The DRCs clean the information and ensure the system is viable at each stage.
Socrates tooling works together seamlessly to deliver an intelligent system design flow
CoreSight Creator system is sensitive to a change in information. If, for example, a newer version of the STM is introduced to the system all you have to do is re-harvest the IP-XACT and a new HLS is generated with the updated system information. This allows users to modify their design using an iterative loop that has had the time and pain removed from it. The potential for optimisation is significant as you can get the microarchitecture you desire.
When the iterative process for optimization is finished it is a simple task to generate deliverables. A click of a button is all it takes to build and generate the RTL, testbenches and test environments for the subsystem. It allows you to rapidly configure the system to match the actual target system elements. This info can be utilised back in the Socrates DE as the user interface is aware of all of the interfaces and HLS of the CoreSight subsystem and it just brings that to a SoC-wide level. There is no need for users to manually stitch the CoreSight to the rest of the system itself, it’s done automatically.
It not only creates CoreSight debug and trace – RTL, IP-XACT – but the example test environments as well There’s a lot of visualisation built into the tooling. For the HLS and microarchitecture there are schematics that show you what is happening at this stage. There is also a schematic for the RTL design.
At this stage the CoreSight debug and trace subsystem has been generated and is ready to be integrated with the rest of the SoC. The Socrates DE can now harvest the CoreSight information and use it as part of the greater system assembly process.
Insert ARM IP into your design at the click of a button with Socrates
Socrates DE features an IP Catalog that contains the IP-XACT information of all the ARM IP that a partner has licensed. It means that, for example, a partner can simply include any Cortex processor and CoreLink System IP into the system. While it is the best available tool for ARM IP, Socrates DE is vendor-agnostic, meaning it can handle any 3rd party and proprietary IP block by harvesting its IP-XACT description.
All of the IP Tooling provide real ARM integrated systems that are right first time. They intelligently integrate ARM IP, 3rd party IP and subsystems into the overall SoC with a methodology that dramatically reduces the design cycle. This saves time for system architects, allowing them to differentiate their SoC while maintaining design integrity.
With the release of the CoreSight Creator and CoreLink Creator, designers will no longer need extensive experience of the architecture to generate a debug subsystem or system interconnect that is optimized for their requirements. Its system intelligence makes it possible to configure an entire subsystem in a matter of days. By increasing the ease with which these highly configurable IP blocks are put together, it allows users to realise all of the performance advantages they contain. Previously, too often, available optimizations were overlooked due to time pressures to get the design taped out.
The IP tooling suite is being officially launched at DAC on June 8-10 at the Moscone Center in San Francisco. If you’re in the area then check out ARM at Booth #2428 to see live demonstrations of the tools. Find out more about the ARM presence at DAC.
Useful links for further information:
New ARM IP Tooling Suite Reduces SoC Integration Time from Months to Days
Whitepaper: IP-XACT Standardized IP Interfaces for Rapid IP Integration
Whitepaper: Solving Next Generation IP Configurability
Whitepaper: Lessons from the field – IP/SoC integration techniques that work
Socrates IP Tooling webpage