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10 Useful Facts about Cortex-M System Design Kit (CMSDK)

Joseph Yiu
Joseph Yiu
November 8, 2013
3 minute read time.

The Cortex-M System Design Kit (CMSDK) is an extremely useful product for chip designers and FPGA designers working with the ARM Cortex-M processors. It contains a wide range of AMBA bus infrastructure components, example systems, example peripherals, verification components and synthesis scripts. Below are 10 facts about the CMSDK which might be useful to you.

10 Facts about CMSDK

1. Choices

There are two editions of CMSDK. The full version of CMSDK provides a wide range of bus infrastructure components to support designs with mixed 64-bit and 32-bit AHB, and provide bus bridges to connect between bus segments of different clock speeds. If you are doing simple system designs with the Cortex-M0 or Cortex-M0+ processors, you can use the smaller Cortex-M0 System Design Kit which provides essential components for building simpler systems.

Cortex-M0 System Design Kit variations diagram

Figure 1: Two versions of the CMSDK product

2. Flexibility

Many of the components in CMSDK are already configurable using Verilog parameters. In addition, the CMSDK license terms allow you to modify the CMSDK examples systems and components to fit your applications.

3. Support multiple bus masters

Both full versions of CMSDK support designs with multiple bus masters. A easy to use 3-to-1 master multiplexer is available in both versions. A configurable AHB bus matrix is available in the full version of the CMSDK, which allows up to 16 master ports and 16 slave ports, and enables concurrent accesses by multiple masters to multiple slaves.

4. Verification components

The CMSDK includes various verification components, for example the AHB Lite bus protocol checkers. They are typically used in simulations for detection of bus protocol violations. They can also be of use in assisting formal verification.  Another useful verification component is the File Reader Bus Master, which is for generating bus transfer stimulus in simulations, including scenarios that cannot be generated with a processor.

5. Advanced features in AHB to APB bridge

The synchronous AHB to APB bridge component allows you to run the APB bus segment at the same frequency as the AHB, or at a divided clock ratio. It also has a bus status output which can be used to gate off the clock signal for the peripheral bus when no transfer is taking place. This enables much lower power consumption.

AHB to APB bridge

Figure 2: AHB to APB bridge enables gating of peripheral bus clock

6. Asynchronous bridges support

There is an asynchronous AHB Lite to APB bridge in the full version of the CMSDK, that allows the APB bus segment to run at a completely different clock frequency. Similar to the synchronous version, it also has the bus clock gating control output signal.  An asynchronous AHB to AHB bridge was added to the kit in revision 1 of the design kit.  This bridge component also provides an optional APB port so that you can bridge two bus segments with one bridge component.

7. Robust system design 

There is an AHB timeout monitor and an APB timeout monitor in the design kit. The monitors can be coupled to bus slaves directly and return an error response if the bus slave is stalled and cannot return a response within a certain number of clock cycles. This prevents a fault in a bus slave from locking up the whole processor system.

8. Tool support 

CMSDK is designed to support a wide range of tools, e.g. Mentor Modelsim/Questasim, Cadence Incisive/NC Sim, Synopsys VCS, ARM Compilation tool chain, Keil Microcontroller Development Kit (MDK), and gcc.

9. Easy SRAM integration

CMSDK has an AHB Lite to SRAM bridge component which enables on-chip synchronous SRAM to connect to AHB with no wait states. In addition, there is also an external SRAM memory interface module which supports 16-bit and 8-bit SRAM or external peripherals.

10. Easy design migration

If you are migrating peripherals from 8-bit or 16-bit architectures to ARM, the example bus slaves in the CMSDK are easy to understand examples of how to interface peripheral registers to AHB Lite or APB. The designs of the example slaves are partitioned into bus interface modules and register blocks. You can reuse the bus interface module directly to connect most of you legacy peripherals to AHB Lite or APB.

 AHB/APB interface modules in CMSDK example slave

Figure 3: AHB/APB interface modules in CMSDK example slave can be used as bus wrappers for legacy peripherals

More Information

More information of the CMSDK can be accessed by clicking on the link below, and details of the components in CMSDK are available in the Technical Reference Manual.

Cortex-M System Design Kits overview

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