Introducing Arm GICv5: a scalable, hypervisor-free interrupt controller for modern multi-core systems with improved virtualization and real-time support.

A high-level introduction to the Arm Architecture Machine Readable Specification (AARCHMRS) Features.json with some examples to interpret and start to work with the available data using Python.

Arm and 9elements Cyber Security have brought a prototype of OpenBMC to the Arm Neoverse Compute Subsystem (CSS) to advancing server manageability.

How to synchronize JIT-compiled instructions across threads.

How to implement `__clear_cache` using assembly.

Read about the different user space delays and wait implementations for the Armv8+ architecture and best practices for the purpose of improving throughput and fair access to shared resources.

.NET 9 introduces SVE support on Arm, allowing users to write simplified vectorised code. This blog post gives examples in C# and compares it to C++.

Supporting C++ style exceptions and DWARF for Pointer Authentication Codes (PAC) signed pointers.

Utilizing Pointer Authentication Codes (PAC) and Branch Target Instructions (BTI) together and optimizations in instruction counts.

This post will show how Linux developers can enable Pointer Authentication Codes (PAC) and Branch Target Instructions (BTI) them in C/C++ code bases.

How vendors can reduce cost and adapt to longer product lifecycles with an updated, compliance-based Arm SystemReady programme.

Arm's 2024 v9.6-A extensions introduce significant updates to enhance computing performance, efficiency, and security for today’s AI enabled software.

The SVMATCH instruction in Arm SVE2 accelerates multi-token string matches, boosting performance in tasks like JSON decoding.

This blog post explores three video and image use cases demonstrating the proven impact of the Armv9 CPU architectural features.

This blog post describes how to implement the same matrix-matrix multiplication algorithm using three different Arm technologies: Neon, SVE, and SME.

This blog is the second half of a two-part blog for SME Instructions. See link to Part 1 in the note at the top of this blog post.

This blog series provides an introduction to the Arm Scalable Matrix Extension (SME) including SVE and SVE2.

Upstream gem5 and ATP-Engine MPAM-style cache partitioning are discussed, with experiments for the feature being proposed and analyzed.

This blog covers techniques and tips that are useful to create better performing programs through compilers whether you are creating Android, Desktop or Server applications.

In-depth analysis of what the PMU of L2D_CACHE_WR counts on the Neoverse N2 server.

We refer to the SPE performance methodology whitepaper published by Arm for details on the content of this blog.