Using Cache Coherency to Verify the AMBA4 Protocol
The Jasper User Group Meeting was held on November 8 & 9 and was full of presentations on the diverse ways that users are applying formal techniques — some in areas where never before thought possible…
big.LITTLE and AMBA 4 ACE keep your cache warm and avoid flushes
Updated 29th October 2013High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM's big.LITTLE proces…
Simplifying SoC's with Hard Macros - New solutions for old problems
At the TSMC Open Innovation Platform (OIP) forum in San Jose this week Mike Inglis, the General Manager of the Processor Division at ARM, presented a keynote speech succinctly titled "Enabling Smart System…
Energy Efficiency and Air Conditioning - Part 1
I've recently realized just how similar mechanical and electronic engineering are when it comes to energy conservation. You see, I've recently begun construction of an energy-efficient, Frank-Lloyd Wright…
Avoiding rush hour traffic jams in your SoC design
Thank goodness for the new packetization, virtual networking and clock gating features of the ARM CoreLink NIC-400. I'm fed up with hearing about spurious comparisons between a single humungous crossbar…
Designing an ARM Based SoC: How to Meet Your Power Budget
ARM IP and ARM processor usage is pervasive across multiple segments of the electronics industry. As shown in Figure 1, each of these market segments have unique design challenges and analysis drivers…