instructions fetch

Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots...
instructions fetch

Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots...
Instruction Fetches from Peripheral Memory Space

Is it possible to use the MPU to configure the Peripheral Memory Space as Execute? It looks possible via the MPU_RBAR.XN bit. If this is the case, is it fair to say that TrustZone aware select gates...
Instruction Fetches from Peripheral Memory Space

Is it possible to use the MPU to configure the Peripheral Memory Space as Execute? It looks possible via the MPU_RBAR.XN bit. If this is the case, is it fair to say that TrustZone aware select gates...
Cortex-A8 : instruction fetch for dual-issue

Hi, We experiment the following loop code (runs 4096 iterations) and we get CPI=0.66 (in other words, loop initiation interval (II) is about 6 machine cycles). We are trying really hard to reason why...