L2C-310 Cache Sync

Hi, I’m a little bit confused regarding the atomic operation Cache Sync (REG7_CACHE_SYNC). How should the maintenance operation used? I have seen an example in XILINX SDK. void Xil_L2CacheFlush...
L2C-310 Cache Sync

Hi, I’m a little bit confused regarding the atomic operation Cache Sync (REG7_CACHE_SYNC). How should the maintenance operation used? I have seen an example in XILINX SDK. void Xil_L2CacheFlush...
Cortex-A9 MPCore with L2 Cache Controller (L2C-310)

Note: This was originally posted on 16th July 2012 at http://forums.arm.com On a quick introduction note, I am working on Cortex-A9 with MPCore configuration where Number of cores is 1. We have L2C- 310...
Cortex-A9 MPCore with L2 Cache Controller (L2C-310)

Note: This was originally posted on 16th July 2012 at http://forums.arm.com On a quick introduction note, I am working on Cortex-A9 with MPCore configuration where Number of cores is 1. We have L2C- 310...
L2C-310 double linefill issuing

Hi, I have a problem to understand the functionality of double linefill issuing. In which case the cache controller loads a second cache line from L3 into L2? Where is the difference to prefetch?...