LDM/STM interruption of Cortex-M7.

Hi Cortex-M7 specialists. I would like to know the Cortex-M7 behaviors when requested interrupts. In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be...
LDM/STM interruption of Cortex-M7.

Hi Cortex-M7 specialists. I would like to know the Cortex-M7 behaviors when requested interrupts. In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be...
ldm/stm with not aligned 4byte

Hi experts! I want to use ldr/str or ldm/stm to copy memory not aligned 4bytes. I know their input address should be aligned by 4 bytes. but is there any solution to use ldr/str or ldm/stm though src...
ldm/stm with not aligned 4byte

Hi experts! I want to use ldr/str or ldm/stm to copy memory not aligned 4bytes. I know their input address should be aligned by 4 bytes. but is there any solution to use ldr/str or ldm/stm though src...
AXI transaction when ldm/stm instruction used on cortex-a9

Note: This was originally posted on 15th September 2011 at http://forums.arm.com HI, ARM experts I used ldm/stm instruction to copy(read-write) memory with caches disabled. The code is listed as: int...