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    Hi We have an MMU-500 ARM IP being used in one of our SoCs. As part of the cluster level verification, we need to preload the TLBs, pagetables etc of MMU-500 IP. We have a few queries regarding this...
  • How to invalidate cache (NVIDIA Drive PX2, ARMv8)
    Hey, on our development board we use PCIe to exchange data between the two Tegras on a NVIDIA Drive PX2 . Basically the data coming across NT ports acts like a DMA engine writing to system RAM. With...
  • Can I place the System MMU (SMMU-400) before the DRAM Memory Controller (DMC-400)?
    Hi all,   I have two A15 CPUs and 1GByte of DRAM memory. I want to dedicate 0.5GByte of memory to each CPU. Would the following system work?   (A15)  (A15)    |          | ----CCI-----        |     SMMU...
  • ARM cortex M4
    Which Linux version used for ARM cortex M4 ?? and how to install this linux version on TDA3x from Texas instruments ??
  • Does Aarch64 LDTR behave differently in secure vs non-secure?
    Can LDTR be used to test requests from secure EL0 or are all results taken in the context of NS EL0?