• GIC500 :: How to forward interrupts to multiple cores using GICD_IROUTER
    Is there a way to forward the interrupts from Descriptor to multiple Cores using GICD_IROUTER ? Seems the Affinity Routing field in my case is hard-tied to 1. P.S. The SoC I'm working on, do have...
  • GIC 500 :: Not able to find the definition for GICD_IROUTERn register
    Can someone please point me to the documentation where I can find the definition for GICD_IROUTERn register. I see it mentioned in DDI0516B_gic5000_r0p0_trm but not the complete definition.
  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?
    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt. I am a software engineer. My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1? This question...
  • about affinity routing in GICv3 (can't understand a figure in the document)
    I was reading the document "GICv3_Software_Overview_Official_Release_B.pdf". In page 8, I see this figure. it shows for each GIC version, how the modes are set by the registers for each exception...
  • GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0
    Hi, I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0. How to test: GIC3.0: 1. read timestamp(t01) 2. core0 write ICC_SGI0R_EL1 to trigger...