• How to understand Exclusive Transaction failure conditions in CHI?
    The purpose of Exclusive Access is to read, calculate and modify a cache line atomically. The built-in Atomic Transactions can do some basic calculations at ICN or SN, but if more complex operations are...
  • Finding design errors before it’s too late
    What are Design Reviews? Design Reviews are a service offered by Arm whereby expert engineers visit our partners to perform a detailed review of a particular stage of the design cycle. Based on that...
  • AXI transaction
    Axi master initiating the incr transfer of length let's say 15 means there is total 15 write transfer are there of 4 byte on 32 bit data bus. So now does AXI slave update the memory just after getting...
  • Question about AXI Exclusive Access Process
    Let's think about the case that a master issues a exclusive write transaction to a slave. On the AXI Specifiaction document, it says that if the slave doesn't support "Exclusive Accesss", then it will...
  • ARM CHI Issue C Specification - Can we receive DataSepResp, RespSepData in any order at a CHI Requester Node?
    Can we receive RespSepData, DataSepResp in any order at a CHI Requester Node? and if a DataSepResp is received before RespSepData will it be considered as a valid Response of the Request, Should the Request...