• what action will be performed by the master based on the read and write responce in axi 4?
    i read the specification of AXI 4 protocol. i want to know what action will be performed by the master when it receive okay,exokay,slverr or decerr. okay and exokay says that the transfer is completed...
  • Is during AXI unaligned transfer not all WDATA bits used?
    Dear Forum, Can you please confirm one thing. When we have un-aligned transfer, do some of WDATA bits not used during that transfer? For example, in the below unaligned transfer WDATA[7:0] are not...
  • AXI Wrap burst address calculation, start_addr=0x96h, burst_size=8transfers each of 4 bytes wide
    Hello, I am unable to understand , which start address should i take in case of wrapping burst address calculation of AXI? For example , my Burst size=4 transfers(beats) each beat(transfer)size...
  • [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
    Hello, A couple of further details on the question. Let's assume that I have a 64-bit data bus and a 32-bit address bus. A master issues a WRAP burst with AWADDR[31:0] = 32'd8 and AWSIZE[2:0]...
  • AXI-4 questions
    Hello, I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these. 1) I would like...