• Regarding WRAP burst calculation in AXI4
    Could you please help me on this topics in AXI4 protocal :: 1. what is meant by Aligned and Unaligned address? 2.How can I calculate WRAP boundary calculation in AXI4? please explain with example...
  • Axi4 Write Transaction
    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.
  • Is there a limit for AXI4 outstanding transaction?
    Hi all! I'm working on an avalon to axi4 master writing bridge module. In many cases,I need to assert a large number of awvalid continually for writing efficiency(for instance, a frame of 4K video data...
  • AXI4 - read data interleaving
    Hi Folks, We need a clarification on Read Data Interleaving on AXI4 Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving: Multiple Read commands can be executed...
  • Removal of WID's in AMBA AXI4
    Hi , What is the purpose of removing ID's (WID) in AXI4 ? If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please...