• How to handle clean operation in Data Cache
    Hi, I have a question. when a processor sends a clean request to data cache, how data cache should behave? 1. does it need to evict all cache lines present in cache (including clean lines) or does...
  • ARM Linux: Can I control cache flush and invalidation in user space?
    These days I'm using Xilinx SoC to design a software, which shares memory between Cortex-A cores and FPGA. I've tried reserve memory in Linux and mmap() /dev/mem. The problem is if I use O_SYNC, it very...
  • ARMv8-64 Cache management in a PSCI functions
    Hi everyone, I'm currently working on type-1 hypervisor and would like to provide support of the ARM Power State Coordination Interface. http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D...
  • ARM CoreLink MMU-500 System Memory Management Unit - Preloading the TLBs and page tables
    Hi We have an MMU-500 ARM IP being used in one of our SoCs. As part of the cluster level verification, we need to preload the TLBs, pagetables etc of MMU-500 IP. We have a few queries regarding this...
  • SMMU emulator/simulator
    Hi ! At the moment, the only SMMU I have on real hardware does not provide an address translation mechanism, only a way to control the NS bit of DMA transactions. In order to prepare for a more...