• Questions about Barrier instructions & ACE Barrier transactions
    1. How barrier instructions like `dmb ishld` and `ldar/stlr` translate to ACE barrier transactions? I am curious about how barrier instructions which will only affect specific types of memory operations...
  • AXI5: AtomicCompare transactions.
    Hi all, After reading the AXI5 specification, I ran into some doubts regarding the AWLEN of AtomicCompare transactions. As per the specification, we can have AWLEN > 0 which ultimately means we can...
  • barrier instructions Vs. barrier transactions
    I have several questions about barrier operarions. 1. how to operate barrier instructions ISB, DMB, DSB in ACE?      a) when ISB is executed, what are the signal values about barrier transaction  (AxBAR...
  • burst-based transactions on AXI
    Hi, I'm confusing with burst transaction in AXI. there is one key feature in AXI spec.... > "burst-based transactions with only start address issued" How can we understand this point? ...
  • RE: In read or write transaction in AXI.what happen if data transaction  is before address.
    Hii, In AXI 3 if data items are written before the address comes due to register delays .....then where that data is being stored in memory because no address is being specified till now...? please...