• ACE protocol : Eviction and snoop request at same time
    How to handle below scenario ? At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high) At same time t1...
  • Interrupt Routing flow in GICv3
    Hi all, GIC is quite an interesting topic and interrupt controller can also be said as an most important module in an SoC that routes interrupts to the Processor. We know that there different interrupt...
  • GIC500 :: Not able to disable Affinity Routing
    I'm not able to disable the affinity routing (i.e. ARE_S and ARE_NS bits being set always). Reset value of GICD_CTLR register is 0x30. Actually I want to forward the interrupt from Distributor to multiple...
  • How interrupts are routed in EL3/EL2/EL1 mode
    Sorry for basic question, For ARM64, we have different interrupt vector table for each mode EL3/EL2/EL1 I am wondering, how a specific IRQ is routed to given mode. in GIC, I am not able to find...
  • AXI transaction
    Axi master initiating the incr transfer of length let's say 15 means there is total 15 write transfer are there of 4 byte on 32 bit data bus. So now does AXI slave update the memory just after getting...