• [APB] Assert timing of PSTRB and PPROT
    Hi All, I have a question about assert timing of PSTRB and PPROT. I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted. I guess these signals...
  • APB4 PSTRB
    I want to know if it is possible to use pstrb = "0101", "1010" or "1001"
  • When should APB slave Sample address/Data for read/write transaction from APB master?
    I am working on design of APB master and slave connected back to back. Slave component has simple reg with 16 locations As per APB, for READ/WRITE transaction from master I am generating PSEL = 1 in...
  • Axi4 Write Transaction
    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.
  • why PSTRB signal in APB4 have four bits?
    PSTRB signal indicates which byte lanes to update during a write transfer. it shows that the bus contain valid data, when PSTRB[3:0]=1111. why we need bus instead of single bit PSTRB signal?