• AXI narrow read with unaligned address
    Hi, I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario: - 32 bit data bus - address x0001 - length 0 (1 beat...
  • AXI fixed burst to a slave with narrow data width
    Hi, I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3 )to an address 0X100 of the slave? Would the...
  • burst-based transactions on AXI
    Hi, I'm confusing with burst transaction in AXI. there is one key feature in AXI spec.... > "burst-based transactions with only start address issued" How can we understand this point? ...
  • AXI Read Transaction Dependencies
    What if RVALID is asserted before the ARVALID and ARREADY, and also RREADY has been already asserted?
  • AXI4 Burst Transactions
    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction. Eg. Burst length- Two , Burst size 16 bytes. Please give me answers...