• What sort of visibility does a non-secure debugger have of the secure sections?
    This question was raised in the ' How to implement a secure IoT system on ARMv8-M ' webinar, view all the questions in the round up blog post .
  • GIC-400 non-secure access
    Hi, experts I'm the new one porting armv8 linux. I have some problem about gic400 access. In the porting linux progress,CPU will switch to EL1NS. In gic_dist_init() function, I read the the  GICD_ISENABLERn...
  • Is it possible to set a memory region from non-secure to secure at runtime?
    This question was raised in the ' How to implement a secure IoT system on ARMv8-M ' webinar, view all the questions in the round up blog post .
  • Can secure states know that they are in secure state?
    I am developing OP-TEE in secure EL1. My architecture is AArch64, ARMv8 However, I want to prove to others that my code is running in secure EL1, rather than non-secure EL1. Am I able to do that? ...
  • Interrupt status in Aarch64
    Hello, In Cortex, A9 CPU register CPSR tells the current execution mode , bit M[3;0] I am looking for if there is similar register present in A64 architecture . Reading ESR_EL3/EL2/EL1, I think...