• Bypassing all clock gates in Cortex-R52 (ARMv8)
    Hello, (#context): I have a Cortex-R52 in the SoC design. My team is in charge of FPGA prototyping of the entire/part of the SoC. I am prototyping (on FPGA) part of the SoC which has the R52 plus...
  • FVP Cortex R52
    Hello, I'm using the FVP Simulator with the Cortex R52 model. Is there any documentation specific to the Cortex R52? I cannot find a suitable memory map in the fast_models_fvp_rg_100966_1100_00_en...
  • How to map tag RAM banks to data cache lines in Cortex-R5?
    Hi, We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data...
  • Freescale Adopts Cortex-M to Address Exponential Electronic Content Growth in Vehicles
    Yesterday in Shanghai, Freescale Semiconductor made a significant announcement to bring their Kinetis EA series of MCUs into the automotive market . Thus far, ARM’s success in automotive has mainly been...
  • New online training course – Arm Cortex processor behaviors
    We are very pleased to announce a new online training topic – Arm Cortex processor behaviors. About the course This course builds on our series of topics that introduce the A, R, and M profiles of...