• Barrier Transactions in ACE
    Can somebody please explain how barrier transactions in ACE work? Thanks in advance.
  • barrier instructions Vs. barrier transactions
    I have several questions about barrier operarions. 1. how to operate barrier instructions ISB, DMB, DSB in ACE?      a) when ISB is executed, what are the signal values about barrier transaction  (AxBAR...
  • AXI5: AtomicCompare transactions.
    Hi all, After reading the AXI5 specification, I ran into some doubts regarding the AWLEN of AtomicCompare transactions. As per the specification, we can have AWLEN > 0 which ultimately means we can...
  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?
    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt. I am a software engineer. My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1? This question...
  • AXI transaction
    Axi master initiating the incr transfer of length let's say 15 means there is total 15 write transfer are there of 4 byte on 32 bit data bus. So now does AXI slave update the memory just after getting...