• GIC 500 :: Not able to find the definition for GICD_IROUTERn register
    Can someone please point me to the documentation where I can find the definition for GICD_IROUTERn register. I see it mentioned in DDI0516B_gic5000_r0p0_trm but not the complete definition.
  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?
    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt. I am a software engineer. My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1? This question...
  • Other core's view after writing ICC_SGI1R_EL1 to trigger SGI
    For example, the codes are executed in core0. codes: (1) send SGI to core1 ICC_SGI1R_EL1 (2) set(a) = 1 i) Then the core1 will first see the irq or the change of variable a? ii) If I add ISB...
  • GIC500 :: How to forward interrupts to multiple cores using GICD_IROUTER
    Is there a way to forward the interrupts from Descriptor to multiple Cores using GICD_IROUTER ? Seems the Affinity Routing field in my case is hard-tied to 1. P.S. The SoC I'm working on, do have...
  • GIC500 :: Not able to disable Affinity Routing
    I'm not able to disable the affinity routing (i.e. ARE_S and ARE_NS bits being set always). Reset value of GICD_CTLR register is 0x30. Actually I want to forward the interrupt from Distributor to multiple...