• Navigating SoC Verification with Perspec Portable Stimulus
    Gone are the days when you used to use manual navigation aids to move around the town. Opening the Global Positioning System (GPS) to public use enticed technology firms to provide automation in navigation...
  • CHI protocol cache line states
    The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states...
  • The Technical and Business Side of Custom SoCs vs. Discrete IC Boards
    New data shows that the break-even, return on investment (RoI) point continues to fall as custom SoCs compete directly with traditional discrete IC board designs. By jblyler , Editorial Director, JB Systems...
  • White Paper: Custom SoCs Compete with Discrete IC Boards
    In this White Paper, commissioned by ARM, author and leading industry commentator John Blyler ( jblyler ), takes a look at the current economics of custom System-on-Chip development relative to discrete...
  • Cache in SOCs
    Dear Sir/Ma'am, In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. I know processors...