• AMBA 5 CHI Memory Attributes
    CHI-B Spec Page number 2-93 states that writes must not be merged in the device memory type description. I am unable to understand: a) What is this merging? b) How to merge different writes? Also...
  • AMBA 5 CHI Streaming ordered WriteUnique Txn
    As per the CHI-B Spec Page number: 2-71: The figure 2-24 shows the Streaming ordered WriteUnique transaction flow. It says that this flow prevents a read acquiring the new value of write-B before write...
  • Error in AMBA 5 CHI spec?
    P189, 5.2.1 Dataless transaction without memory update Why does RN-F0 transition I->UC, rather than UCE or UD? After MakeUnique, RN-F0 has obtained the right to modify the cache line by discarding all...
  • ARM CHI Issue C Specification - Can we receive DataSepResp, RespSepData in any order at a CHI Requester Node?
    Can we receive RespSepData, DataSepResp in any order at a CHI Requester Node? and if a DataSepResp is received before RespSepData will it be considered as a valid Response of the Request, Should the Request...
  • Behaviour of CHI Receiver during race condition from RUN to DEACTIVATE
    It is mentioned in CHI Specification that when the transmitter is deasserting LINKACTIVEREQ, to move from RUN to DEACTIVATE, for the receiver, it is required to accept flits both before and after the...