• GIC v3&4: Programming sequence of GIC Registers
    Hi., Is there any sequence in programming GIC Registers. Physical Interrupts point of view, I have followed sequence as follows: GICD GICR GICC/ICC Coming to Virtual Interrupts point of view, I had small...
  • GIC-400 non-secure access
    Hi, experts I'm the new one porting armv8 linux. I have some problem about gic400 access. In the porting linux progress,CPU will switch to EL1NS. In gic_dist_init() function, I read the the  GICD_ISENABLERn...
  • GIC virtualization -- GICH_ELRSR and hardware interrupts
    Consider a hypervisor injecting a hardware interrupt in a virtual machine, by setting the HW bit in a List Register (LR). According to the GICv{2,3,4} specification, after the virtual machine has taken...
  • HREADY when no activity on bus
    Hello, We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave. ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control...
  • Can secure states know that they are in secure state?
    I am developing OP-TEE in secure EL1. My architecture is AArch64, ARMv8 However, I want to prove to others that my code is running in secure EL1, rather than non-secure EL1. Am I able to do that? ...