• GICR_WAKER.ChildrenAsleep conditions to go to 0x0, post PE power-up
    As stated in GIC v3 Arch: After powering up a PE, software must set ProcessorSleep to 0 and wait until ChildrenAsleep == 0. Can you please also state the conditions for GICR_WAKER.ChildrenAsleep to...
  • [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface!
    Hi all, I am investigating the GIC Stream protocol and having a confusing issue as the title. The figure below shows the case that an interrupt is retrieved from CPU interface. As explained in...
  • Configuration to generate FIQ interrupts on ARMv8
    I want to know what is the GICv2 configuration to map an interrupt to FIQ and signal it to the ARM core and the configuration on the ARMv8 to raise that FIQ interrupt at EL1 exception level.
  • The non-secure copy of the GICC_CTLR gives FIQEn bit as reserved. How to configure GIC to generate FIQ in this case?
    In the the arm gic arch specification  (version 2) section 3.9.2,   it has been given that for any implementation of GICv2 (with or without Security Extn) we can configure the GIC to generate FIQ for...
  • GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0
    Hi, I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0. How to test: GIC3.0: 1. read timestamp(t01) 2. core0 write ICC_SGI0R_EL1 to trigger...